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buzzwords [2010/11/17 22:30] lsubrama |
buzzwords [2010/12/01 23:06] (current) lsubrama |
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| ===== Lecture 19 ==== | ===== Lecture 19 ==== | ||
| - | + | Main memory system | |
| - | Main memory system | + | |
| * Memory hierarchy | * Memory hierarchy | ||
| Line 355: | Line 354: | ||
| ===== Lecture 21 ==== | ===== Lecture 21 ==== | ||
| - | Super scalar processing (I) | + | Super scalar processing I |
| * Types of parallelism | * Types of parallelism | ||
| Line 374: | Line 373: | ||
| ===== Lecture 22 ==== | ===== Lecture 22 ==== | ||
| - | Super scalar processing (II) | + | Super scalar processing II |
| * Trace Caches | * Trace Caches | ||
| Line 455: | Line 454: | ||
| * history based predictors | * history based predictors | ||
| * two-level predictors | * two-level predictors | ||
| - | ==== Lecture 25 ==== | + | ===== Lecture 25 ==== |
| Control Flow - II | Control Flow - II | ||
| Line 471: | Line 470: | ||
| * Perceptron branch predictor | * Perceptron branch predictor | ||
| - Perceptron - learns a target boolean function of N inputs | - Perceptron - learns a target boolean function of N inputs | ||
| + | * Call and Return Prediction | ||
| + | * Indirect branch prediction | ||
| + | - Virtual Conditional Branch prediction | ||
| + | * Branch prediction issues | ||
| + | - Need to know a branch as soon as it is fetched | ||
| + | - Latency | ||
| + | - State recovery upon misprediction | ||
| + | * Predicated execution | ||
| + | |||
| + | ==== Lecture 26 ==== | ||
| + | Control Flow - III & Concurrency | ||
| + | |||
| + | * Predicated Execution | ||
| + | - Predication decisions at the compiler | ||
| + | - Rename stage modifications | ||
| + | * Limitations of predication | ||
| + | - Adaptivity | ||
| + | - Complex Control Flow Graphs | ||
| + | - ISA support | ||
| + | * Wish branches | ||
| + | - Wish jump/join | ||
| + | - Wish loop | ||
| + | * Wish branches vs Predicated Execution | ||
| + | * Wish branches vs Branch prediction | ||
| + | * Diverge-Merge Processor | ||
| + | * Dynamic-Hammock | ||
| + | * Multi-path Execution | ||
| + | * Research issues in control flow handling | ||
| + | - Hardware/software cooperation | ||
| + | - Fetch gating | ||
| + | - Recycling useful work done on wrong path | ||
| + | Concurrency | ||
| + | * Classification of machines | ||
| + | - SISD | ||
| + | - SIMD | ||
| + | - MIMD | ||
| + | * Decoupled Access/Execute | ||
| + | * Astronautics ZS-1 | ||
| + | * Loop unrolling | ||
| + | |||
| + | ==== Lecture 27 ==== | ||
| + | VLIW | ||
| + | |||
| + | * Each VLIW instruction - a bundle of independent instructions (identified by compiler) | ||
| + | * Each instruction bundle executed by hardware in lockstep | ||
| + | * Commercial VLIW machines | ||
| + | - TIC6000, Trimedia, STMicro | ||
| + | * Intel IA-64 - Partially VLIW | ||
| + | * Encoding VLIW NOPs | ||
| + | * Static Instruction Scheduling for VLIW | ||
| + | * Code motion - Safety & Legality | ||
| + | * Trace scheduling | ||
| + | * List scheduling | ||
| + | * Super block scheduling | ||
| + | * Hyperblock scheduling | ||
| + | * The Intel IA-64 architecture | ||
| + | - No lock step execution of a bundle | ||
| + | - Specify dependencies between instructions within a bundle | ||
| + | - Template bits | ||
| + | * What hinder static mode motion? | ||
| + | - Exceptions | ||
| + | - Loads/Stores | ||
