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project [2010/10/29 14:33] vseshadr |
project [2010/12/09 17:55] (current) lsubrama |
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| * [[http://www.microarch.org/micro42/|Micro]] | * [[http://www.microarch.org/micro42/|Micro]] | ||
| * [[http://www.cse.psu.edu/hpcl/hpca16_files/program.html|HPCA]] | * [[http://www.cse.psu.edu/hpcl/hpca16_files/program.html|HPCA]] | ||
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| + | ====== Project Deadlines ====== | ||
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| + | * Milestone 2 Deadline: **Midnight November 10th**. Please submit your report though blackboard in a pdf format. **Do not forget** to list your names in the pdf document as well as during submission (blackboard interface). | ||
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| ==== Group 2 ==== | ==== Group 2 ==== | ||
| Names: Anoop Ramakrishna, Kartikeya Goyal, Tejas Chopra\\ | Names: Anoop Ramakrishna, Kartikeya Goyal, Tejas Chopra\\ | ||
| - | Title: Cost-Benefit Analysis of thread Scheduling Algorithms on ACMP\\ | + | Title: Scheduling of Critical Sections on ACMPs with Multiple Large Cores\\ |
| Points of Contact: 1st=Lavanya, 2nd=Evangelos | Points of Contact: 1st=Lavanya, 2nd=Evangelos | ||
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| ==== Group 14 ==== | ==== Group 14 ==== | ||
| Names: Alexey Tumanov, Joshua A. Wise \\ | Names: Alexey Tumanov, Joshua A. Wise \\ | ||
| - | Title: Tilera ManyCore - Memory Controller Affinity & Execution Placement \\ | + | Title: Variable Memory Controller Latency Mitigation for Many-core \\ |
| Points of Contact: 1st=Lavanya, 2nd=Vivek | Points of Contact: 1st=Lavanya, 2nd=Vivek | ||
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| ==== Group 16 ==== | ==== Group 16 ==== | ||
| Names: Bin Fan, Lin Xiao, Prashant Kashinkunti \\ | Names: Bin Fan, Lin Xiao, Prashant Kashinkunti \\ | ||
| - | Title: A Micro-Architecture Level Study of FAWN Architecture\\ | + | Title: Caching/Prefetching for Cloud Computing Applications\\ |
| Points of Contact: 1st=Vivek, 2nd=Evangelos | Points of Contact: 1st=Vivek, 2nd=Evangelos | ||
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| ==== Group 18 ==== | ==== Group 18 ==== | ||
| - | Names: Wei Lin, Yu Wang, Daniel Lin\\ | + | Names: Wei Lin, Yu Wang\\ |
| Title: Concurrent Critical Section Access Acceleration: a Hybrid System of Speculative Lock Elision and Asymmetric CMP architectures\\ | Title: Concurrent Critical Section Access Acceleration: a Hybrid System of Speculative Lock Elision and Asymmetric CMP architectures\\ | ||
| Points of Contact: 1st=Evangelos, 2nd=Lavanya | Points of Contact: 1st=Evangelos, 2nd=Lavanya | ||
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| ==== Group 19 ==== | ==== Group 19 ==== | ||
| Names: Rohit Banerjee, Tim Detwiler, Alekh Vaidya \\ | Names: Rohit Banerjee, Tim Detwiler, Alekh Vaidya \\ | ||
| - | Title: Task-Aware Scheduling for Multi-Core Memory Interconnect\\ | + | Title: Memory-Access Aware Task-Aware Scheduling for Multi-Core Systems\\ |
| Points of Contact: 1st=Evangelos, 2nd=Lavanya | Points of Contact: 1st=Evangelos, 2nd=Lavanya | ||
| \\ | \\ | ||
