About 18-760 VLSI CAD: Logic to Layout




	is our best shot at answering all the questions students typically want to ask about 18-760, from basic logistics to more philosophical stuff.

	When and where is class? Tue-Thu from 12:30 to 2:20, in HH B131. Oh, and yes, the lectures really do go 2 hours sometimes, but we take a break in the middle when the oxygen in the room starts to get thin.
	Who is teaching 760? Professor is Rob A. Rutenbar, office HH3105, phone x8-3334, email rutenbar@ece.cmu.edu, office hours 2:30-5:00 Tuesdays and by appointment. Secretary is Lyz Knight, office HH3107, phone x-8-5087, email is lyz@ece.cmu.edu. TA this semester is Amit Singhee, office HH3104, phone x8-6646, office hours 2:30-5:00 Fridays.
	What are the text books? Synthesis and Optimization of Digital Circuits, McGraw-Hill, 1994, Giovanni DeMicheli is used for the logic synthesis material. Also, lots of lecture notes and suppmentary readings are handed out.
	What is the class about? 18-760 is a CAD course aimed at graduate students and serious seniors who want broad exposure to the algorithms and data structures inside modern VLSI design tools. 18-760 is basically an applied algorithms class, where the application is VLSI design. We focus on the class of designs called Application Specific Integrated Circuits, or ASICs, where the goal is to go from a high-level design (think: Boolean equations and state machines) down to a mask layout (think: rectangles) both correctly and quickly. The set of tools you can use to do this is called a tool flow. Synthesis tools move forward in the design: they actually design stuff, and add details. Verification tools check each step, making sure what you just designed is actually what you intended to design. The assumptions about how you are allowed to design a chip--and they are numerous--constitute the design methodology. In modern designs, methodology, individual design tools, and chips themselves all evolve in parallel. To understand what's interesting in CAD today, you have to understand a basic CAD methodology. In this course, we look at the "big" tools along the path from logic to layout for ASICs.
	What exact topics are covered? We have about 15 weeks of lectures, with topics organized more or less like this: Introduction to CAD flow for ASICs Advanced Boolean Algebra Boolean Representation and Manipulation: BDDs Formal Verification: Finite State Machine Equivalence Logic Synthesis: 2-Level Forms Logic Synthesis: Multi-Level Forms Technology Mapping Static Timing Analysis for Logic Networks Intro to ASIC Layout Network Partitioning by Classical Algorithms Component Placement for ASICs Component Routing for ASICs Electrical Timing Analysis for Interconnect Data Structures for Dynamic Layouts Layout DRC and Extraction
	What is the class NOT about? It's not a circuits class--although we will mention circuits a few times. It's not a digital design class or VLSI design class, in the sense that we design a system or a chip. Instead, we design software for CAD tools. But it's not just a hacking class: there is some nontrivial math to explain what our CAD tools are doing.
	What are the prerequisites? 15-211, 15-212: Basic CS data structures and algorithms, programming in C and UNIX. 18-240: Basic digital design and verification, combinational and sequential logic. Some exposure to VLSI ideas: for example, a basic digital electronics class, such 18-322.
	Are we hacking in C or C++ ? Mostly C++ these days-- learning C++ is a good thing by now. This semester we will continue to teach & use some JAVA, too.
	What is the relation to the 18-360 undergrad course? 18-360 is not a prerequisite for 18-760. 18-360 is our undergrad CAD offering. Folks who took 360 can take 760, and there will be a few topics of overlap: some basic BDD stuff, Kernighan/Lin partitioning, basic annealing, maze and channel routing, some test ideas. For BDD manipulation, network partitioning, ASIC placement and routing, 760 will overlap but do more detail and more algorithms than you saw in 360. Unlike 360, we don't devote any time to ASIC testing ideas.
	Are there other related CAD courses at CMU? Yes, a bunch of them. As well as 18-360 Computer Aided Digital System Design, which is aimed at undergraduates and taught by Prof. Don Thomas, we also offer several grad CAD courses, including: 18-761: VLSI CAD: Layout to Manufacturing. Sister course to 760, offered (usually) each spring, covers the electrical side of CAD: simulation, numerical algorithms, device modeling, yield modeling, TCAD. Taught by Prof. Andrzrej Strojwas. and Dr. Tamal Mukherjee 18-762: Circuit Simulation. Offered every other year, covers more advanced aspects of logic, circuit, timing and interconnect simulation. Taught by Prof. Lawrence Pileggi. 18-763: Phsical CAD for VLSI. Offered occasionally, covers more advanced aspects of layout synthesis, analysis, and estimation. Taught by Prof. Rob Rutenbar. 18-765: Digital System Testing and Testable Design. Offered every Fall, covers more advanced aspects of testing, fault modeling and simulation, and design for testability. Taught by Prof. Shawn Blanton 18-767: VLSI CAD: Software to Logic. New course, offered this Fall, covers system-on-chip design issues, in particular hardware/software tradeoffs, modeling, codesign. Taught by Prof. Joann Paul and Prof. Don Thomas. 18-743: Energy Aware Computing. Another new course, offered this Fall, focusing on energy/power issues in design. Taught by Prof. Diana Marculescu.
	What are the assignments, grade policy? 6 Homeworks: analyze and design CAD algorithms and small programs to illustrate core CAD ideas. 3 Projects: Programming assignments to build CAD software in JAVA and in C,C++/UNIX. 3 Paper reviews: analysis of topics from the CAD literature. Grading: 40% homework, 45% projects (5%-20%-20% for projects 1-2-3), 15% papers.
	What is the policy on working in groups? Homeworks and paper reviews you do alone. On some projects you will be allowed to work in groups--we will tell you when. It's OK to talk about the class and the assignments with your friends. It's not OK to just copy their work. Cheating and plagiarism will be punished according to CMU's standard procedures.
	What is the policy on late assignments? Late assignments are only accepted with permission of instructor. You lose 10% of your points per day late (yes, weekends count), up to a max of 7 days late, after which we won't take it. So, for example, if you would have got an 80/100 on an assigment, and you hand it in 3 days late, you get 80 * 0.30 = 24 points subtracted.
	*What the heck* are all those pictures on the 760 homepage? [We ask forgiveness, gentle reader, while we attend to the metaphorically challenged... RAR] This is a course about tools**--VLSI tools of course, but tools none the less. Some of the issues involve methodology: the way chip design decisions and software tool decisions depend on each other. One of the ways CAD folks think about this is the plumbing of the tool flow: how decisions and constraints flow from the start to the end of the design. This course strives to cover both the science stuff: algorithms and such, and the plumbing: flows, nuts and bolts of methodologies, and so on. Now, was that so obscure...?