The most significant risk that could jeopardize the success of this project is whether we can successfully meet the timing requirements with our Verilog design. This problem can only be verified once we complete the CPU design, then we do timing analysis on those to see whether it is possible. If that is not possible, we would try optimizing our critical path or we may switch to some other processors. However, switching another processor means we might have to switch the target of the emulation for this project. Currently, we have not planned to make any change to our project design.
Carnegie Mellon ECE Capstone, Spring 2026 | Bert Shan, Jingchu (Jacob) Xu, Yunhao (Michael) Zhang