This week, I focused on hardware integration and synchronizing the rendering pipeline with the CPU core. I worked on integrating the PPU’s sprite-zero hit logic with Bert’s 6502 CPU core. This is a critical timing feature that allows the software to detect when the first sprite, which is typically part of the status bar, is rendered, enabling the split-screen scrolling effects seen in games like Super Mario Bros.
On the physical hardware side, I soldered a DC voltage regulator to our NES controller interface. This modification allows the Arty Z7-20 to safely and directly drive the controller’s 5V logic levels from the FPGA’s 3.3V I/O pins. Following this, I collaborated with Jacob to map the controller input states to the specific OAM and PPU registers in the Programmable Logic via the AXI-Lite interface.
I am currently on schedule, and for the following week, I will finalize the PPU scrolling logic to handle mirroring, which is required for different game cartridges. I will also conduct stability testing on the visual debug overlay to ensure it does not interfere with the main rendering timing during the interim demo.