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Bert’s status report 3/14

This week I completed verification of the MOS 6502 CPU RTL implementation for all legal instructions. I validated the CPU core using autogenerated test cases to ensure correct functional behavior across the instruction set.

I also finished the architectural design of the PPU, including defining its main functional blocks and how it will interact with the CPU and memory system.

Currently, I am implementing the PPU modules and working on establishing the interface between the CPU and PPU. I am also exploring ways to ensure proper communication and synchronization between the two components.

Next week I will continue implementing and debugging the PPU and focus on integrating it with the CPU to validate their interaction.

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Jacob’s Status Report for 3/14

Acquired and tested the newly arrived Arty Z7-20 boards. Previous issues with the Zedboard are resolved. Validated ROM loader correctness. Validated CPU official opcode correctness with both simulation and hardware. Set up PPU validation workflow with Mesen2 as the golden model. Implemented HDMI video output (not yet connected to the NES core).

I am currently on schedule. Next week, aside from continuing the validation for the PPU, I’ll start to add the controller inputs and the UDP syncing algorithm.

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Michael’s Status Report for 3/7

This week, my efforts focused on moving from internal logic to visual output for the 2C02 PPU. I worked on the sprite rendering pipeline, which now successfully integrates the OAM priority logic with the pattern table fetching mechanism I developed previously. This allows the hardware to correctly handle the transparency and palette selection for up to eight sprites per scanline.

For the upcoming week, I aim to work on the VGA-to-PPU coordinate mapping and demonstrate a static pattern table display on a monitor.

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Bert’s status report 3/7

Finished 6502 CPU core implementation, supports all instructions for MOS 6502. Tested the implementation with autogenerated testcases, remain to work on validating the CPU with official test cases from Klaures. CPU also needs to test for timing issues. Started implementing and debugging PPU implementation. For next week continue to work on PPU and validating CPU implementation

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Jacob’s Status Report for 3/7

Finalized the design and completed the design review. Completed the code for controller input. Ready to pick up the ordered board next Monday and test the ROM loader, AXI-lite interface, and controller inputs.