Bert’s Status Report for 2/7

For this week, I did some research and study on the 6502 processor and instruction set. I found other open-source projects that have demos on simulation of the processor and attempted to test them on VCS and Icarus Verilog. The main issue that I found and made progress through is how to convert assembly 6502 assembly code to bytecode and provide them to the CPU test bench. I have also studied through the structure of the 6502 processor to understand how the code works.

The progress is on schedule, we plan to complete the main CPU and run tests on those during the first few weeks, what I did is some progress on this step. For the next week, the goal is to run all the tests for the CPU, pass them and try to synthesize through Vivado, and do some timing analysis.

Team Status Report for 2/7

The most significant risk that could jeopardize the success of this project is whether we can successfully meet the timing requirements with our Verilog design. This problem can only be verified once we complete the CPU design, then we do timing analysis on those to see whether it is possible. If that is not possible, we would try optimizing our critical path or we may switch to some other processors. However, switching another processor means we might have to switch the target of the emulation for this project. Currently, we have not planned to make any change to our project design.