Mihail’s Status Report for 03/21

I spent most of the week debugging the RTL for the FIR filter component, and implementing infinite impulse response (IIR) filtering. The primary difference between FIR and IIR filtering was that IIR filtering also considers past output values as well as prior inputs, increasing the number of weights that needed to be stored as well as the number of steps in the adder tree. I decided that it was simpler to maintain prior values for both X[n] and Y[n] as shift registers, rather that storing them in BRAM, since, based off of my research, IIR filters do not need to store a large amount of terms. The bookkeeping circuitry eliminated by moving to a sliding window approach seems to outweigh using registers instead of BRAM to store prior input / output wave data. With audio output configured correctly, I also looked into verification. I began writing testing scripts in MATLAB to generate “golden models” for various filters / on board components, mainly looking at the Signal Processing Toolbox. The main question remaining is how to properly capture output from the FPGA synthesizer itself, a problem which I hope to solve in the following week so that we can perform some validation / refinement before the interim demo.