I spent most of this week with my teammates preparing for the upcoming interrim demo. For the first half, I realized that there was a core issue with how I was implementing frequency modulation earlier and decided to redo it based off of articles I found online, mainly, I now use two oscillators. The first is the baseline that is already used to perform wave table lookup, and the second oscillator is used to modulate the first. I am still in the process of debugging this and do not believe it will be done before the demo, but I plan on running simulations and comparing outputs to matlab scripts – one of the standard testing processes as described in our design report.
The second half of the week was spent on adding delay to the actual FPGA and debugging. The delay module was added into the pipeline after ADSR. A major bug was output amplification, it turned out that I was incrementing the feedback gain too rapidly. This seemed to cause the output amplitude to rapidly reach its maximum, causing a very unpleasant noise to constantly be emitted from the FPGA. I am still trying to understand the source of the issue, but clamping the value of the feedback coefficient g was enough to resolve it. I still plan to spend tomorrow gathering data in order to better understand the cause of the issue, so that I can avoid it for other filters. I intend to spend next week further debugging FM, and hopefully beginning to add in FIR and IIR filters.