Mihail’s Status Report for 02/14

This week I spent my time with the team, preparing the design presentation. I spent much of my time focused on the solution approach for the FPGA internals, particularly our audio processing pipeline. Additionally, I worked on creating a plan for testing and verification, looking at how we could numerically compare our digital output to a golden model, and responded to some feedback from the TA regarding the presentation. After next week’s presentations, I hope to get started on implementing the RTL for the frequency modulation and applying the ADSR envelope.