Risk Identification and Mitigation Strategies
Primary Risk Concern: A major risk for this project is choosing an acceptable FPGA to support our hardware acceleration constraints. Which FPGA we choose is important, we want one that has enough logic elements to support our RTL implementation.
Mitigation Strategies:
To address this risk before any potential issues, we are planning on using an FPGA in the project inventory (we are planning on using the DE10-Standard at the moment since Cyclone V has much more support than Cyclone IV boards). Since there is only one of these boards in the project inventory at the moment, we can pivot to ordering another Cyclone V board online if the DE10-Standard is claimed by another team (we are considering this less costly FPGA: https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=218&No=1021&PartNo=2#contents). This will be a significant portion of our budget but our required items for purchase are not as expensive as this FPGA, so we will still be well within budget even if we need to purchase another FPGA.
Design Changes:
Although we have not made changes to our design yet and will continue to discuss this on Monday, we are working to incorporate feedback from our proposal. We are considering changing our design to from being entirely wired to including wireless communication where necessary to improve our scalability. We are currently exploring our options still, but we are primarily looking at bluetooth.
Schedule Change:
After the proposal presentations, we realized that our Gantt chart wasn’t accounting for spring break, so we decided to change that and include a time for break. Note that the RTL implementation task likely will not be worked on during spring break, but we thought that it wouldn’t be as clear if we separated the same task into two different tasks.
