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Team Status Report for 2/10

Risk Identification and Mitigation Strategies

Primary Risk Concern: A major risk for this project is choosing an acceptable FPGA to support our hardware acceleration constraints. Which FPGA we choose is important, we want one that has enough logic elements to support our RTL implementation. 

 

Mitigation Strategies: 

To address this risk before any potential issues, we are planning on using an FPGA in the project inventory (we are planning on using the DE10-Standard at the moment since Cyclone V has much more support than Cyclone IV boards). Since there is only one of these boards in the project inventory at the moment, we can pivot to ordering another Cyclone V board online if the DE10-Standard is claimed by another team (we are considering this less costly FPGA: https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=218&No=1021&PartNo=2#contents). This will be a significant portion of our budget but our required items for purchase are not as expensive as this FPGA, so we will still be well within budget even if we need to purchase another FPGA. 

 

Design Changes: 

Although we have not made changes to our design yet and will continue to discuss this on Monday, we are working to incorporate feedback from our proposal. We are considering changing our design to from being entirely wired to including wireless communication where necessary to improve our scalability. We are currently exploring our options still, but we are primarily looking at bluetooth. 

 

Schedule Change: 

After the proposal presentations, we realized that our Gantt chart wasn’t accounting for spring break, so we decided to change that and include a time for break. Note that the RTL implementation task likely will not be worked on during spring break, but we thought that it wouldn’t be as clear if we separated the same task into two different tasks. 



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Brian’s Status Report for 2/10

Accomplishments

Simon and I researched FPGA hardware acceleration and discussed our results briefly in order to understand how it works to a better degree and we also deliberated on which FPGA would be good to use for our project. While we saw multiple articles online where Xilinx FPGAs are being used for accelerating ML algorithms, we came to the conclusion that the exact type of FPGA doesn’t really matter and we decided that we could use an Intel Altera board (currently planning on using the DE10-Standard, can order the DE10-Lite if the DE10-Standard is taken by another team). We also found that it would be better to use a Cyclone V FPGA rather than a Cyclone IV FPGA like the DE0-Nano, because Cyclone V boards support OpenCL, which is a framework we are heavily considering for hardware acceleration. 

 

Furthermore, I came across this article that seems to be very relevant for our project (https://www.researchgate.net/publication/338481306_Hardware_Acceleration_of_Computer_Vision_and_Deep_Learning_Algorithms_on_the_Edge_using_OpenCL). This article seems to implement hardware acceleration for computer vision algorithms using OpenCL, a high level synthesis framework that converts kernel code to RTL. An even more relevant detail in this article is that this was all done using a Cyclone V Altera board, which we are planning to use by requesting from the project inventory (DE10-Standard). I also edited the Gantt Chart to better reflect our workflow during Spring Break.

 

Project Schedule and Progress

Fortunately, my progress is on schedule, and during Monday’s mandatory lab meeting, Simon and I will discuss our findings in more detail and start working on the design of our RTL/kernel code implementation, if time allows. This portion of the project is extremely important because our approach for hardware acceleration is vital for our final product. 

 

Goals for the Next Week

In the next week, Simon and I hope to finish designing our RTL/kernel implementation and getting an FPGA. I will also hope to complete a significant portion of the cashier time detection algorithm implementation in that time, and we hope to get cameras delivered so we can test our CV algorithms in the future.