This week I was primarily working with Ziyi on getting the code in the C++ build environment to work well with the Vitis HLS build. We spent a while improving the portability of the code as Vitis has a set of specific requirements, and does not work well with very modern C++ code that is generic for many purposes. Vitis HLS has very cryptic error messages, so progress is steady but slow on getting this to work. There is a lot of trial and error involved in figuring out what is causing errors, and it is tricky to figure out how to redesign the code to fix it. We also began to work on optimizations for the fluid simulation, initially by starting to unroll loops, which creates larger parallelism and hardware utilization.
I think that we are on track to complete our project on time, but slightly behind where I would like to be at this point. It is good that we left ample slack in our schedule. Next week I want to continue to work on optimizing the implementation, and also work with Alice on communication between the FPGA and CPU to display the output of our renders.