Last week we were rushing to finish the build for the interim demo, and I was unable to complete the evaluation script. This week I was able to do so. I also read up a lot on unrolling, pipelining, and other optimizations outlined here: https://docs.xilinx.com/r/en-US/ug1399-vitis-hls/HLS-Pragmas
This upcoming week I’ll be working on adding said pragmas for optimizations. I’ll also be helping to verify that the Vitis HLS project provides reasonable fluid simulation output once Ziyi finishes the interface work to get an output text file from the FPGA.
We had a really great push at the beginning of this week. I’m optimistic that we can achieve our goals.