Ziyi’s Status Report for 03/26/2022

At the start of this week, Jeremy and I managed to get the C simulation build to pass in Vitis HLS. While we were quite happy at this initial success, we quickly realized that we still needed a lot more work to get the C synthesis working. One thing that majorly complicated this task was that the C synthesis build script would fail pre-synthesis without actually printing any errors. However, after poking around on the Vitis forums and ticking some specific compilation boxes, we could finally read some of the error logs. As it turns out, most of our problems were just version and build conflicts with different C++ features. For instance, while we were able to get away with the auto function type for our lambda functions in simulation, the synthesis compiler got a bit angry at us. Right now, we are still trying to resolve these issues and hopefully synthesize some version of the kernel soon.

In the process of fixing these compilation errors, we also got started on our optimization work. One major task that we did this week was that we got rid of all instances of par_for, seq_for, and for_n, which – respectively – iterated a function over the particles parallelly, iterated over the particles sequentially, and iterated over the neighbors of each particle. This is a major step, as it allows us to manually control the unroll parameters of the kernel on a per-loop basis, rather than applying a single pragma en masse.

Other than slowly grinding through the myriad waves of compilation errors, there is nothing too much to schedule and to report. Still, once we get a working build of the binary, we’ll throw it onto the FPGA and get some timing values reported. We’ll also need to get a survey of the resource utilization of the base implementation. We envision that this will be done by next week.

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