This week, we made progress on two fronts. On the hardware front, Jeremy and Ziyi worked on getting the Vitis HLS build to work on the stripped down version of Scotty3D; on the software front, Alice worked on having Scotty3D read particle postions from a preloaded file for stepping through a simulation.
In terms of hardware, we managed to get the C simulation build option to work and run a small testbench. While this was a good start for getting the binary built, we realized that we still had a long way to go before we could get C synthesis to work. The biggest hurdle is that the C synthesis seems to run on an older version of C++, with a bunch more restrictions and caveats on what can actually get compiled into hardware. Many features that the C simulator readily worked with, the C synthesis just outright refused to cooperate with. Still, despite these setbacks, we believe that we are quite close to a breakthrough for the C synthesis. Once we finally get a working build, we will get the area estimates and also get some timing reports from putting the binary on the Ultra96 development board and running it. It is also worth noting that in our endeavors to get a working build, we alsorefactored the par_for, seq_for, and for_n (for neighbors) lambda functions into separate, discrete for loops. Though this reduces code reuse, it is important in that it allows us to specifically reconfigure the different instances of these loops so that we can more deliberately assign hardware resources as opposed to accelerating all of the different loops with the same parameters (which would otherwise be hard coded in the lambda functions themselves).
In terms of the Scotty3D interface, we were successful in getting Scotty3D to run a precomputed set of points. Of course, this resulted in a lightning fast visual simulation within the Scotty3D engine, which provides a compelling example of the benefit of hardware accelerated precomputation. Nevertheless, though this is not as interesting as a real-time demo, it is a significant step in the right direction. The next major goal on the interface side is to enable UART communications between the FPGA and a host computer to transfer live simulation data. This will be an essential step to having the real-time simulation. Of course, we will also have to investigate the UART bandwidth to see if we can keep up with frames per second latency demands of the simulator.