This week I implemented all the SystemVerilog code needed for Ethereum mining. This included the mining module, the FPGA module to accept Ethereum puzzles from the Raspberry Pi and the module to send completed Ethereum nonces to the Raspberry Pi. I also created testbenches for these modules in order to test their functionality through simulation. While the mining module still needs some debugging, the communication ones appear to be working as intended. In addition to this, I also synthesized this full design with Quartus onto an FPGA. The FPGA can take in a bitstream through the GPIO pins and store the puzzle in its internal memory. Once the mining modules find a correct nonce, it outputs this through the GPIO pins as a bitstream as well.
In terms of my schedule, I am a little behind on getting the Ethereum code working. The mining module is causing some issues that I still need to fix. I still have not been able to test the Bitcoin communication modules because the Raspberry Pi side of this is not working properly. Until this issue is resolved and that part of the project is functional, I will focus my attention on getting Ethereum working.
Next week I hope to test the Ethereum modules more rigorously on the FPGA. This includes connecting reset wires from the Raspberry Pi and testing configuration switching. I will also hook up LEDs to our breadboard as an interim way to test communication while the Raspberry Pi code is being worked on.