This week I created the framework for the SystemVerilog testbenches that I will use to test the communication modules. For the communication module, I hooked up the module ports in the testbench file and added randomized testing inputs as well. I haven’t run the test with VCS yet because we are still finalizing the bit widths of the module inputs. Additionally I also finalized the design for the communication module and added functionality that allows it to recreate the Bitcoin puzzle from a single bit data input. The top module containing the communications now has buffers that are able to store this puzzle and replace it with a new puzzle when needed. I anticipate being able to run this implementation along with the testbench next week.
Next week, I will synthesize the design as well in order to fulfill the second part of our testing plan. The FPGAs have arrived already so I can load it onto the board to test with the switches. I am still on schedule to finish my portion of the code including the communication module next week. However, I placed an order for the Raspberry Pi about 1.5 weeks ago and still have not heard back. The software we need to test on the RPI is still in hiatus. I will speak with the course staff if I haven’t heard back by next week.