Tag: status report

Jolin’s status report for 4/24/2021

I took a slow week after getting a ton of things done last week for the interim demo. I had to fly back to Pittsburgh to move house and take care of all the lease-ending chaos. I had limited access to a working environment.

I am a little behind schedule but with the mental planning of the arpeggiator I have already done, I should be able to catch up this weekend and early next week.

Hongrun’s Status Report for 4/24

This week I focused on two items:

  • Finish simulation testing on ADSR envelopes: I ran a simulation using vcs to validate that my code for the ADSR functionality is working.
  • Planned verification and testing for the entire system: I reviewed our design material to look for parameters that I need to test for in the verification and testing phase. This included correctness metrics, such as whether the waveforms we produced are the same as that we have obtained using matlab scripts; how much do the pitches produced by our synthesizer vary from the 12-equal temperament standard; how much delay there is from the time the FPGA gets a signal to the time that a signal is played via the DAC as an output…

I am a little behind this week, since the original plan was to get the ADSR synthesized, but I only managed to get the simulation working.

Next week I will,

  • Synthesize the ADSR module to get and integrate it with the rest of the system
  • Carry out the verification and testing on campus using oscilloscopes. This might take a little effort because I am not so familiar with the trigger function, but I will try my best to get the numbers for my teams so that we could present these on the week of 5/3.

Team Status Report for 4/10/21

This week our team has worked a lot on integrating the implemented functionalities. Jiuling worked a lot on this aspect by refactoring our repository. A significant problem that occurred this week was that the current clock rate (50MHz) is too fast for memory access needed for the sine wave oscillator. We will try to resolve this issue by using a slower clock (25MHz or 12.5 MHz).

There is a slight cost of latency to this change, but since we set a pretty loose goal for latency (10ms), we are still on a good track of hitting this metric.

In addition, all three members have started on checkpoint three tasks and our team is overall on track for this week. However, we anticipate that lots of work will need to be done in the following week as we will prepare for the interim demo and finish up on our checkpoint three tasks simultaneously.

Michelle’s status report for 4/10/21

This week, I worked on writing code for the unison detune effect (branch). I did some research online about the actual application of unison detune in commercial synthesizers, and I learned some of the different parameters and modes for configuring the effect. For one, the spacing between the detuned frequencies and the central, original frequency could be designated as:

  • standard: where the spacing is the same throughout, like: | | | | |
  • exponential: where the spacing increases as the difference between the frequency increases, like: |   |||   |
  • inverse logarithmic: where the spacing decreases as the difference between the frequency increases, like: ||   |   ||

Since we are only using one rotary knob to control the unison effect, we were not planning to implement multiple modes. I decided to write my implementation as the exponential mode, because from what I heard from some of the examples online, the resulting sound given by this mode has the most potential, and it sounds the closest to our expectation of the unison detune effect.

I am on schedule so far. My stereo decoder is still on its way, and it will hopefully arrive soon. After receiving the necessary board elements for playing audible sound, I will be able to tune the parameters more easily. Next week, after integration, we will be done with our third checkpoint. After that, we can start on our fourth checkpoint of implementing the arpeggiator effects.

Jolin’s status report for 4/10/2021

  • This week I spent a ton of hours writing full system integration and the progress is shown in this pull request. (The pull request shows some older commits but the main progress was made earlier this week).
  • The project structure is now much more clear. I decoupled the hardware interfaces from the core system with a clear division of responsibility. The ChipInterface connects the core system conFFTi to hardware PLL clock, data read in from UART driver and send the audio out to the DAC driver. This setup isolates the core system logic from the hardware interface, so in the future if we want to use a different FPGA board or use a different audio codec, all we need to do is to change the device drivers without modifying the core system.
  • The system also becomes easily configurable. I defined all the configuration constants in one file. It’s super easy to change all system configurations from the output audio bit width to the number of polyphony support all by just changing the numbers in this file.
  • The code for each subsystem is organized into its own folder: midi, dispatcher, pipeline, and mixer. Each subsystem comes with its own unit test suite for all the modules. To make life easier, I standardized the testing procedure with the Makefiles (rule definition, file dependency). Testing is now much less painful.
  • My work concludes checkpoint 2 of our project.

I am on schedule.

I received the new TRS to MIDI cable and DAC controller with the headphone jack today. Next week I will be working on the arpeggiator control.

Hongrun’s Status Report for 4/10/21

This week I focused on developing the ADSR module due for our third checkpoint. I looked into the triangle wave oscillator code because conceptually the A, D, and R stages should be implemented in a similar fashion to the triangle wave oscillator. After I am done with the development I will move onto writing a testbench and use the generated waveform for affirming the correctness of the program.

As far as progress goes, I am on track.

Next week, I will focus on the following:

  1. Continue developing the ADSR module
  2. Get the project to synthesize on a lower clock rate (See more about this in the team status report)

Michelle’s status report for 4/3/21

This week, I finished running simulations of the waveform oscillator of all four types of waves and merged my code (one of the commits). I also fixed some issues within the code, for example, I was using multiple clocks in always blocks.

However, synthesis on the board is not compiling successfully when my teammate tried to do so. I took time to set up the synthesis environment on my local machine, and I will try to look into the issue.

Because of the hardship we faced in using the MIDI breakout board, I also did some investigation on connecting the MIDI keyboard directly to the FPGA via USB.

I am on schedule. Next week, we will be moving into the third checkpoint. I will try to get different sounds playing from the four types of waveforms, then I can start on the implementation of the unison effect.

Team status report for 4/3/21

This week, we used one week out of our planned slack time because we were experiencing hardships in the hardware interface between MIDI and the FPGA. We wanted to take time this week and try to get the hardware working before moving on to our next checkpoint. The main reason for this difficulty is the fact that the cable that we bought for connecting the MIDI to the MIDI breakout board isn’t functional. So, instead of processing our MIDI input with MIDI –> breakout board –> FPGA, we decided to go directly from MIDI to FPGA with a USB connection. Fortunately, we were able to get MIDI signal transmission working via USB, and we are actually able to hear audible output from a DAC.

We have updated our Gantt chart to reflect this change in schedule.

Jolin’s status report for 4/3/2021

This week I paused from arpeggiator control and focused on DE2-115 audio CODEC control and USB control instead. IMHO the readability and quality of the demonstration code that came with DE2-115 CD are rather low. It took me a town of effort to look past the typos (e.g. adio_codec) and dead code (i.e. wall of code working with signals that has nothing to do with output signal). Although I can generate Altera IP modules and understand how to use simple ones, I can’t get the whole control to work. Luckily, the PLL modules that I did understand can be integrated with Hongrun’s effort of using GPIO for MIDI input and audio DAC output.

We have adjusted our timeline last week to account for the difficulty we faced with the FPGA IO.

This weekend I will be integrating all the code we have so far for our checkpoint 2. Next week I will start to code the arpeggiator control.

Hongrun’s Status Report for 4/3/21

This week I did the following:

  1. Got the MIDI interface circuit to work with a new TRS cable
  2. Got the DAC circuit to work

Since these are the goals for this week, I met my goals.

I am basically on track after taking a week of slack time to make up. I am happy to get the physical interfaces working and at least get some sounds through our system.

For next week, I will focus on developing the ADSR envelope module.