This week I have mostly wrapped up my part of the project this week by implementing the bonus wavetable oscillator features:
- I wrote a script that converts the .raw files that Michelle generated from an open-source library to .vm formats. I used a module for taking in the .raw files as a stream of 16-bit data samples and then converted each data sample into 24-bit and storing each of them in order in a .vm file because the AUDIO_BIT_WIDTH we set for our project was 24.
- I changed the configuration variables in SystemVerilog so that now it would give our oscillators access to the new wavetables in addition to sqr/sin/tri. This was not that difficult because I was able to reuse a lot of the code in the sqr/sin/tri wavetable oscillator module. Our previous features such as ADSR and PWM will still work on the new wavetables.
- I modified the ChipInterface module to allow our users to choose waveforms from the switches on the FPGA. We would have loved to move this interface onto our keyboard, but we, unfortunately, ran out of knobs to do so.
What is left for next week is very minimal, just mostly merging my code with Jolin’s ongoing progress with the Record and Cycle functionality. I will also help with Michelle’s work on the video and our report together!