This week I focused on two items:
- Finish simulation testing on ADSR envelopes: I ran a simulation using vcs to validate that my code for the ADSR functionality is working.
- Planned verification and testing for the entire system: I reviewed our design material to look for parameters that I need to test for in the verification and testing phase. This included correctness metrics, such as whether the waveforms we produced are the same as that we have obtained using matlab scripts; how much do the pitches produced by our synthesizer vary from the 12-equal temperament standard; how much delay there is from the time the FPGA gets a signal to the time that a signal is played via the DAC as an output…
I am a little behind this week, since the original plan was to get the ADSR synthesized, but I only managed to get the simulation working.
Next week I will,
- Synthesize the ADSR module to get and integrate it with the rest of the system
- Carry out the verification and testing on campus using oscilloscopes. This might take a little effort because I am not so familiar with the trigger function, but I will try my best to get the numbers for my teams so that we could present these on the week of 5/3.