- I now have a fully working simulation and synthesis environment with ModelSim and Quartus, respectively. Making the USB-blaster cable work took me a while since the USB-Blaster on Linux requires some special setup. I spent extra hours debugging the JTAG connection because my laptop’s USB port/USB-A-to-C dongle connection doesn’t work reliably.
- My random number generator module and testbench now pass simulation. The output is verified against the Matlab script.
- I learned how to use algorithmic state machine with datapath, or ASMD. It is closer to the actual Verilog code than FSMD.
- I finished the ASMD of the polyphony control that handles MIDI note messages. This design is sufficient for Ckpt 1 (3/22).
I am on schedule.
Next week I will spend most of the time writing the Design Review Report. I will add control message handling to the polyphony design after Hongrun figures out the list of control messages the MIDI keyboard would generate.