This week I worked with the rest of the group on figuring out the CPU’s design. I found this document which gave accurate timings for each instruction (it is incomplete though as it is a work in progress). With it, we were able to draw a datapath we believe accurately represents the Gameboy’s pipeline. Afterwards, Tess and I tried to figure out implementation details of multi-cycle instructions. We decided to solve this problem with an FSM which would control the different stages of a multi-cycle instruction. The basic idea is to have the FSM divide each multi-cycle instruction into smaller single cycle instructions. We believe this behavior mimics the Gameboy’s behavior best because it has been observed in the emulator community that in the middle of a multi-cycle instructions flags get set multiple times.
On my graphics work, I did some research on the inner workings of the Gameboy PPU. My next action item based on this will be to sketch out a datapath for it so that we can talk about it in the design review and also so I can get started with implementing it. Furthermore, I got the VGA controller working and tested it on the screens in the labs. It has a small bug with the bottom line of the display, I will try to figure it out sometime this week, but it’s not a priority. One thing that I will have to figure out is how to display the Gameboi’s output since the resolution doesn’t match the 640×480 resolution of the lab’s screens. I was thinking of probably having a pixel in the original Gameboy’s screen represent multiple pixels on the screen. This is a discussion for the future.
Action items for next report:
- Make a PPU datapath drawing
- Get the Gameboi decoder and datapath implemented
- Fix the VGA glitch