During spring break and this week, I worked on implementing and fleshing out the FSMs for the multi-cycle instructions. I also created a skeleton for the decoder module, which will work with the FSMs to control the pipeline. For this, I added a new module to our datapath which I thought was necessary to reduce clutter in the FSMs. This module is the FSM manager. It will communicate with the decoder and the rest of the datapath to decide which FSM to use and which of the control signals to use. The plan was to finish the FSM, but I got sidetracked due to recent events.
The goal for this upcoming week is to finish the CPU and start testing it. Tess and I have been starting to look into how to get simulation going and how to instance block RAM to start testing while the SoC component gets developed. I am confident in the progress that we have so far, and hopefully, we’ll finish everything on time.
The other thing I have been planning to pick up is the PPU work, the progress I have so far is the FSM and the skeleton of the main PPU module. I still need to flesh out the sub-modules and start looking into testing it on simulation.
Finally, I plan on going back and cleaning up and commenting on some of the code which is half commented. We got to keep in mind that one of the objectives is to have a well-documented project to help everyone else out in the emulator community who wants to do a hardware emulator.
Goals for next week:
- Finish CPU and start testing
- Clean up and document CPU code.
- Pick up work on PPU again.