This week I managed to get all the information we need to make the PPU. I used various sources to get a good idea of the timings and the overall architecture of the PPU and I think I’ve achieved a good understanding of its inner workings. I used the following sources:
I also browsed through some emulator forums’ threads to check for more specific architecture details about the Gameboy since these docs didn’t mention specific hardware details that could be useful for achieving maximum PPU fidelity. In the end, I decided that it may be a bit hard to get an architecturally accurate PPU representation, so I will just attempt to have one that matches the timings and expected values at each moment.
After this, this is the datapath I came up with:
A PPU “cycle” is divided into 4 stages, these will give the datapath above a bit more meaning:
- OAM Search: In this stage, the sprite fetcher will look for the sprites that are needed for this VBlank stage and put them in the sprite buffer. It can only fetch up to 40.
- Pixel Transfer: In this stage, the fetcher will start fetching tiles from memory and then put them in the pixel FIFO. Since it can fetch a whole row at a time (8 pixels) then the FIFO supports pushing 8 items at once. Based on the registers (which are not shown) the fetching may either fetch sprites, background tiles or window tiles. The pixel FIFO pushes the pixel at the front onto the screen.
- H-Blank: This is the time between each row of the screen. The CPU usually does some work here.
- V-Blank: This is the time between being done with the screen and starting to render the next screen. The CPU usually uses this time to modify VRAM.
I will further expand on these on the design review.
My goals for next week are as follows:
- Start implementing the PPU
- Finish the CPU design and start implementing it.
- Work on the design report.