Team Status Report
RISKS
Our largest risk currently is the lack of coordination between the software and hardware application. Until now Maxwell and Riki have worked separately in order to get their pieces up and running, without discussing much into what actually can be accelerated by the usage of hardware. We plan to spend the next week working on how the two will fit in together, in order to find an optimal coordination.
DESIGN CHANGES
We changed the communication between the SoC (a.k.a. Programmable System or PS) and the programmable logic (PL). We originally designed this communication to be from the PS to shared DRAM, then from the DRAM to the PL where it would be stored in the PL’s block RAM (BRAM). In learning how to implement this design, we learned that Vivado is capable of creating a connection directly between the PS and the PL’s BRAM. This cuts out the extra step of writing to and reading from DRAM, which makes implementation easier and should make the data transfer itself faster. The connection uses AXI, though we don’t have to work directly with this protocol; it is used to communicate between Xilinx IPs which take input from the PS and output to the BRAM. The BRAMs are dual-ported, so we can connect our custom RTL to one port and the AXI IP to the other. From the PS side, the AXI interface appears as a region of memory-mapped IO. A program can perform reads and writes to this region, which have the abstraction of going directly to the PL’s BRAM. This gives us the same easy interface that we would have had had we used our original DRAM design.
Maxwell Johnson
Personal work and Progress:
This week, I researched and implemented the transfer from the PS to the PL’s BRAM described above in Design Changes. Much of the work I’ve done on interfacing to the DRAM is now obsolete, but the time I spent learning Vivado and how to instantiate and interface with Xilinx IPs made it possible for me to quickly implement the new design. For future capstone groups, I would recommend against using tools which you have no experience before (no, using Quartus to program your board in 240 or 341 does not count if you’re going to be working with HLS or an SoC). I have spent a lot of time learning the toolchain for this class, which has been discouraging and has slowed the development of my part of this project.
Deliverables:
For this Monday, John has promised to have a communication channel between the board and the computer established, so in the first half of the week we will make sure that our end-to-end communication is working. After that, I will begin testing a new design for energy computation. By next week, I’ll have a working prototype of this design with a complete interface to the SoC.
John Zhang
Personal Work
Progress
Deliverables
Riki Khorana
Personal Work
This week was all spent on debugging the software written the previous week. There were many subtle bugs that went unnoticed, and I am still working on it.
Progress
There was no major progress last week.
Deliverables
- I am expected to mount the software on the SoC by Wednesday
- I should be initiating the optimization via hardware with Maxwell sometime next week