Team Status Report
RISKS
This week, we had an official schedule slip of about one week. We now risk not meeting our deadlines, and have begun removing tasks and reverting to simpler backup designs. We redesigned our algorithm in light of the press for time and are working on an implementation. When that is complete, we will have addressed our long-standing unknown about how exactly our algorithm will work.
DESIGN CHANGES
We have made a significant change to our algorithmic design on the software side. Whereas we were aiming for a graph-cut approach for identifying seams on the video, we decided to revert back to the incremental dynamic programming approach that we had as a back-up plan.
Originally, the reason for using the graph-cut algorithm was because the dynamic program approach does not ensure an optimal sheet (seam) to be removed when run on a 3D object like a video. Therefore we only had the option to implement the graph-cut algorithm. However after technical considerations such as graph size and run time, we decided that the full graph-cut algorithm was too heavy to be implemented on an SoC + FPGA system. Therefore, we decided to go for the non-optimal but easily accelerated algorithm.
UPDATED SCHEDULE
As mentioned above, we had a design slip. To ameliorate the slip, we condensed our schedule somewhat. We removed user tests entirely from Riki’s schedule. We shifted back Maxwell’s schedule by one week and John’s by two. To accommodate this slip, we cut into the slack time at the end of the project. We have also committed to putting more hours into the project and decided that we would be able to condense the timeline for some of our tasks that do not require interfacing between parts. The updated schedule is here.
Maxwell Johnson
Personal work and progress:
I have spent this week working on interfacing to the memory interface. Unfortunately, after a long week, this goal still eludes me. As expected, interfacing two pieces together has been the most challenging part of the project. My difficulties currently lie in the clock domain. The interface generated by the MIG takes as input a differential system clock (sys_clk_p and sys_clk_n). It outputs a clock signal (ui_clk), which is the clock on which the user design interacting with the interface should run. Right now, it looks to me as though the clock is not running. I am currently trying to make this clock output work. If I cannot, I will determine whether it is possible to generate a clock on my own. The frequency is known (50 MHz, one quarter the frequency of the 200 MHz input to the memory interface), but the phase offset is unknown and I am worried that this may cause unnecessary difficulties.
Deliverables:
With our demo on Monday, I’ll be focused on this issue for the rest of tonight and tomorrow. I am still optimistic that I will have a working interface by then, and implementing a demo will be a welcome break from working on the memory interface. By Monday morning, I still plan to deliver a demo. Following that, I’ll be using the linux interface that John has been working on to load a video into FPGA memory. I plan to finish that by the end of the week. That will be exciting because, once a video can be loaded into memory and read back out, all of the interfaces to and from the programmable fabric will be working, and to complete the accelerator will require only self-contained design. Of course, nothing ever goes to plan, so please stay tuned for the next installment!
John Zhang
Personal Work
My work this week has been focused on getting the SoC ready for the mid-point demo. My goal is to run programs on the SoC that manipulates the DDR3 memory, and thereby achieve communication between the SoC and the programmable fabric.
Progress
My progress was hindered by the fact that I do not have root/administer access to the lab machines. Not running Vivado with administer clearance made it impossible to transfer programs onto the board through JTAG. It’ll have to be through SD card transferring. Therefore instead I set up vivado on my personal laptop to use it with the required access level, and I’m making my way to booting a linux kernel on the board
Deliverables
vivado suite setup on personal laptop.
Hello World program runs on the Zynq boad
Half way through booting Linux on board.
Riki Khorana
Personal Work
My week was split into two parts. The first half was spent understanding and implementing the graph-cut algorithm from this paper. The second half was spent understanding and implementing the dynamic programming algorithm.
Progress
I made progress in the sense that the software application is somewhat ready for the demo on Monday. However I will have to move quickly from now on as the schedule was pushed back a week already.
Deliverables
I will have to refine the software application for the demo on Monday, and start my testing framework construction based on the application I have built.