I started looking into the FPGA acceleration of our chosen chess engine. Chess Programming is a fascinating problem that’s attracted some of the greatest minds in Computer Science, like Ken Thompson. www.chessprogramming.org is the authoritative source of chess programming info. Pretty much all the knowledge I need is held within the pages and third-party links on this wiki.
The problem boils down to a complex search of either all interesting possible moves, or all possible moves period. Back when computation power was limited, heuristics were used to limit the search space of possible chess moves. With the power of Moore’s law, the prominent strategy returned to a brute force search of the “best” move one can make.
I’m planning on using some advanced RTL libraries found in RocketCore for our accelerator. My current game plan is to use unmodified stockfish running on a Raspberri Pi on our first board, with our second board running on an FPGA of some sort. I’m highly skeptical that our FPGA accelerated stockfish will outperform the Raspberri Pi’s 4*A53 Arm Cores @ 1.4 GHZ. But I would be escatic if I can beat it on a clock for clock basis.
First step will be to get Stockfish running on a RocketCore. I’ll need to port Stockfish to RISC-V (which I’m hoping will start as a simple cross-compile). It would be prudent to tune the RISC-V port a bit before I dive into the hardware acceleration. I think the move generation logic is the most ripe candidate for acceleration, while the alpha-beta pruning/search is best left for our softcore.
This is a relatively late addition to our project, so an exact time table isn’t applicable yet. I’ll count this as behind schedule because we’re already pretty deep into the semester and I’m just now starting this. I’ll probably invest some of my spring break working on this project, as it’s directly relevant to what I want to do in my career.
I would to get Stockfish up and running on my ArtyA7-100t FPGA this week. The existing FPGA shell’s and SDK from SiFive should give me a good starting point.
Team Update
The most significant risk at the moment is that I’ll be unable to figure out how the implement the move generation circuit. The literature is all there for me to sift through. This represent’s most of the complexity of the project, so I’ll be doing my best to guide and leverage my other teammates when needed.
We added an FPGA acceleration aspect to our system to make it worthy of an 18500 project. Chess Machine’s aren’t new, so this represents a doable extension to the smart chessboard.
We also need to sit down and redo our schedule now that I have a much more significant burden of the project to investigate. Hopefully we can come up with a revised Gantt chart sometime this week.