This week, our team continued transitioning from system design into active implementation and subsystem testing. Last week, much of our work focused on preparing for the arrival of the development hardware, completing breakout-board designs, and establishing a programming and firmware strategy for the STM32. This week, we began using those preparations to bring up the first portions of the system and verify that the hardware and software architecture we developed earlier in the semester can operate as expected.
A major focus this week was initial bring-up of the STM32 development board. We first verified the basic programming and debugging workflow using ST-Link and SWD, confirming that firmware could be reliably flashed to the processor and debugged through the same interface that we eventually plan to expose on our custom PCB. We then began testing several of the low-level peripherals required for the audio-processing pipeline. Initial firmware tests focused on clock configuration, GPIO, timers, serial debugging, and the peripheral interfaces that will eventually communicate with the audio codec. Establishing this basic firmware environment gives us a stable platform on which the remainder of the audio system can be developed.
We also began implementing and validating the DMA infrastructure that will eventually support continuous audio streaming. Our system is designed around a 48 kHz audio sampling rate and block-based ANC processing, with the current design using 64-sample processing blocks.
Rather than having the processor explicitly move every incoming and outgoing audio sample, DMA will allow the codec and STM32 peripherals to continuously exchange samples while the processor performs signal-processing operations on previously received data. This week, we focused on establishing the buffer structure and DMA transfer model required for this pipeline, including the use of alternating buffers so that processing and audio transfer can occur concurrently.
The next major software milestone is establishing a reliable digital audio path between the STM32 and the audio codec. We began configuring the STM32 SAI/I2S interface and determining the clocking relationships required to maintain the selected sampling rate. Because the codec and processor must remain synchronized throughout continuous operation, correct configuration of the master clock, bit clock, frame synchronization, sample width, and channel ordering is particularly important. At this stage, the goal is not yet to run the full adaptive ANC algorithm, but instead to confirm that known audio samples can be transmitted and received without corruption, dropped samples, or timing errors.
Progress also continued on the audio-codec breakout hardware. The breakout board is intended to allow us to evaluate the codec independently before integrating it into the much more constrained final PCB. Once the board is fabricated and assembled, our bring-up procedure will begin with power-rail and continuity checks before applying power. We will then verify the codec clocking and configuration interface, followed by basic microphone input and speaker output testing. This staged approach follows our planned verification strategy of validating components individually before attempting system-level integration.
On the signal-processing side, we began preparing the existing Hybrid LxFMS simulation for eventual migration onto the STM32. Our MATLAB implementation has already allowed us to study the behavior of the adaptive algorithm, including the approximately 17.88 dB overall attenuation observed in simulation and its stronger performance at lower frequencies.
The next step is therefore not to redesign the algorithm, but to convert the major signal-processing operations into a form suitable for real-time embedded execution. In particular, we are beginning to identify the filtering, vector operations, coefficient updates, and buffer management that can make use of the STM32’s DSP and floating-point hardware.
We are also beginning to establish measurements that will allow us to compare the actual processor against the computational assumptions used during the design phase. Once continuous DMA-based audio streaming is operating, we plan to measure the execution time of each processing block, CPU utilization, interrupt frequency, buffer headroom, and end-to-end audio latency. These measurements will determine how much computational margin remains for the adaptive filter and whether the selected 64-sample block size provides an acceptable tradeoff between processing efficiency and latency. This will be particularly important as we move from simple audio passthrough toward real-time filtering and eventually the complete ANC feedback loop.
Hardware fabrication also continued in parallel with software development. With the breakout designs largely complete, the focus is now shifting toward producing the actual boards and preparing for assembly. This represents an important step because it will allow components such as the codec, microphones, amplifier, and supporting circuitry to be evaluated under conditions much closer to the final system. At the same time, work on the wearable enclosure and physical layout is continuing so that electrical design decisions remain compatible with the eventual sleep-mask form factor rather than being developed independently.
Overall, this week represented the beginning of hardware and firmware bring-up rather than simply preparation for it. The project is now progressing along the implementation structure established during the design phase: testing the processor on a development board, evaluating the codec through a custom breakout board, continuing development of the ANC algorithm, and developing the physical wearable in parallel.
Our primary objective for the next week is to establish the first complete audio path through the system. Ideally, this will consist of microphone or test-signal input through the codec, DMA-based transfer into the STM32, simple processing or passthrough on the processor, and audio output through the codec and speaker. Once this basic path operates reliably, we can begin introducing fixed filtering and then progressively migrate the Hybrid LxFMS algorithm onto the embedded platform.