This week, I focused on beginning the implementation and bring-up of the embedded software that will run on our STM32 processor. With the development boards ordered, I began transitioning from planning the firmware architecture to implementing and testing the low-level functionality required for our ANC system. This included working on the processor’s clock configuration, basic peripheral initialization, and establishing a reliable workflow for programming and debugging the STM32 using ST-Link and SWD.
I also continued developing the DMA-based audio-processing infrastructure that will eventually connect the processor to our audio codec. Our current architecture uses a 48 kHz sampling rate with 64-sample processing blocks, so I focused on designing a double-buffered DMA system that allows audio transfers and computation to occur concurrently. I also began configuring the SAI/I2S peripheral and investigating the clocking and synchronization requirements of the codec. My immediate goal is to establish reliable audio input and output before introducing more computationally intensive filtering operations.
Additionally, I began considering how to benchmark the computational performance of the processor once the audio pipeline is operational. In particular, I plan to measure processing time per audio block, CPU utilization, DMA timing, and overall latency to determine whether our current architecture provides sufficient computational headroom for the Hybrid LxFMS algorithm. My work is currently progressing toward hardware validation, and next week I plan to continue peripheral bring-up and work toward establishing a complete audio passthrough pipeline.