Josh’s Status Report (09/26)

This week, I began RTL implementation of our custom CPU in SystemVerilog, building and verifying the first vertical slice of the datapath. I implemented and tested the general-purpose register file, including byte-register access. I also built an ALU that performs 16-bit ADD and generates all six status flags (carry, parity, auxiliary carry, zero, sign and overflow). It passed over 20,000 directed and reference-model checks. Next, I implemented a decoder subset for MOV r16, imm16 and register-to-register ADD. It consumes instruction bytes through a valid/accept handshake and waits correctly when bytes are unavailable or when execution is not ready. I then built an execution unit that connects the decoder, register file, ALU and writeback through a small instruction controller. The controller retains each instruction’s operation and destination until it finishes. The unit correctly executes a short demonstration program (MOV AX,3; MOV BX,4; ADD AX,BX; ADD AX,AX, leaving AX = 14) and a longer flag-focused program, and it stops safely on unsupported instructions. To check that the tests are meaningful, I injected deliberate bugs into each module and confirmed the testbenches catch them. This also exposed a remaining gap in the execution-unit tests that I will fix. I set up a repeatable local simulation flow with Vivado’s XSim and Make targets for each module, and recorded the test results. I also drafted the CPU-side bus ports (single-byte transactions with explicit completion, plus the interrupt inputs) for review with Ben. The CPU cannot yet fetch instructions from memory, so only these two instruction forms run, fed directly by a testbench. Next week, I plan to review the bus interface draft with Ben. I then plan to build the instruction fetch path (instruction pointer, segment registers, prefetch queue and a minimal bus interface unit) with a simulated memory model, so the CPU can run programs from memory. I will also start extending the decoder and ALU to the full family of arithmetic and logic instructions.