Post your reviews of the assigned papers on the Paper Review Board.

• Go to the Paper Review Board, create an account ('register'), and login.
  
• In the 'collections' page, select 'CMU 18-742: Parallel Computer Architecture – Fall 2012'.
  
• Click 'Subscribe to this collection' and provide the code: ece742

• Go to the Paper Review Board.
• Click the title of the paper you wish to review.
• Near the bottom of the page, click 'add review'.

• Due Sep 11th - Pick two papers from ISCA 2012 proceedings.
  • At least one of them should be new to you.
  • Cannot be a paper you have co-authored.
  • Bonus: pick three papers instead of two.
• Due Sep 11th - NVIDIA Talk: Inside the Kepler GPU Architecture and Dynamic Parallelism.
  • NVIDIA Tech Talk by ECE Alumnus, Philip Cuadra.
  • Monday, September 10, 2012 7-9 pm, HH-1107.

• Due Sep 16th - Suleman et al., “Accelerating Critical Section Execution with Asymmetric Multi-Core Architectures,” ASPLOS 2009. pdf
• Due Sep 16th - Suleman et al., “Data Marshaling for Multi-core Architectures,” ISCA 2010. pdf
• Due Sep 16th - Joao et al., “Bottleneck Identification and Scheduling in Multithreaded Applications,” ASPLOS 2012. pdf

• Due Sep 21st - Smith, “Architecture and applications of the HEP multiprocessor computer system,” SPIE 1981. pdf
• Due Sep 21st - Tullsen et al., “Exploiting choice: instruction fetch and issue on an implementable simultaneous multithreading processor,” ISCA 1996. pdf
• Due Sep 21st - Chappell et al., “Simultaneous Subordinate Microthreading (SSMT),” ISCA 1999. pdf
• Due Sep 21st - Reinhardt and Mukherjee, “Transient Fault Detection via Simultaneous Multithreading,” ISCA 2000. pdf

• Due Sep 30th - Onur Mutlu, “Some Ideas and Principles for Achieving Higher System Energy Efficiency,” NSF Position Paper and Presentation 2012. pdf
• Due Sep 30th - Ebrahimi et al., “Parallel Application Memory Scheduling,” MICRO 2011. pdf
• Due Sep 30th - Seshadri et al., “The Evicted-Address Filter: A Unified Mechanism to Address Both Cache Pollution and Thrashing,” PACT 2012. pdf
• Due Sep 30th - Pekhimenko et al., “Linearly Compressed Pages: A Main Memory Compression Framework with Low Complexity and Low Latency,” CMU SAFARI Technical Report 2012. pdf

• Due Oct 9th - Sohi et al., “Multiscalar processors,” ISCA 1995. pdf
• Due Oct 9th - CALCM Seminar: Scale-Out Processors.
  • CALCM Seminar by Boris Grot (EPFL).
  • Monday, October 8, 2012 10-11 am, CIC 4th floor ISTC - Panther Hollow Room.

• Due Oct 11th - Herlihy and Moss, “Transactional memory: architectural support for lock-free data structures,” ISCA 1993. pdf
• Due Oct 11th - Austin, “DIVA: A Reliable Substrate for Deep Submicron Microarchitecture Design,” MICRO 1999. pdf

• Due Oct 14th - Patel, “Processor-Memory Interconnections for Multiprocessors,” ISCA 1979. pdf

• Due Oct 16th - Moscibroda and Mutlu, “A Case for Bufferless Routing in On-Chip Networks,” ISCA 2009. pdf

• Due Oct 28th - Das et al., “Aergia: Exploiting Packet Latency Slack in On-Chip Networks,” ISCA 2010. pdf
• Due Oct 28th - Dennis and Misunas, “A preliminary architecture for a basic data flow processor,” ISCA 1974. pdf

• Due Oct 30th - Arvind and Nikhil, “Executing a program on the MIT tagged-token dataflow architecture,” IEEE TC 1990. pdf

• Due Nov 1st - Patt et al., “HPS, a new microarchitecture: rationale and introduction,” MICRO 1985. pdf
• Due Nov 1st - Patt et al., “Critical issues regarding HPS, a high performance microarchitecture,” MICRO 1985. pdf

• Due Nov 4th - Kung, “Why Systolic Architectures?,” IEEE Computer 1982. pdf

• Due Nov 13th - Mutlu and Moscibroda, “Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems,” ISCA 2008. pdf
• Due Nov 13th - Kim et al., “Thread Cluster Memory Scheduling: Exploiting Differences in Memory Access Behavior,” MICRO 2010. pdf

• Due Nov 15th - Ebrahimi et al., “Fairness via Source Throttling: A Configurable and High-Performance Fairness Substrate for Multi-Core Memory Systems,” ASPLOS 2010. pdf
• Due Nov 15th - Muralidhara et al., “Reducing Memory Interference in Multicore Systems via Application-Aware Memory Channel Partitioning,” MICRO 2011. pdf