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This week I continued on with research on the 6502. After last week’s discussion, I set out to make a document with microinstructions of each valid instruction + addressing mode combo. This is almost done, with just two instructions left to go now. After this, the processor diagram will be drawn up and there will be much more to start coding with. These are my future goals for this week.
BRK and RTI were really odd cases when drafting up microinstructions. It turns out that documentation does not describe all behavior of the instruction, so I went down a rabbit hole googling and using a cycle-accurate representation of the 6502 to figure out behavior of the BREAK flag in these instructions. I eventually found out that there is no real BREAK flag in the P register. It is almost always set to 1 since PLP and RTI both set the B flag no what processor status they pull off of the stack. So determination of an interrupt being software or hardware based can only be found through bit testing of the value off of the stack, not the value in the P register.
Schedule-wise we are doing fine since we still have a week for the 6502, but I personally wanted to be a bit more ahead with my portion by this time. I intend to work more this weekend to try and meet these personal goals.