On Sunday, Monday, and Tuesday, I spent some time trying to get our FPGA working with the HLS development environment. At first I was working with the Ultra96v1, and I soon realized that much of the configuration for developing on our FPGAs (Ultra96v2) in 18-643 were already set up by the TAs. Thus, for all other FPGAs, I would have to figure out how to set up the board for development. To temporarily remedy this, I asked permission from Professor Hoe (who taught 18-643) if I could borrow an Ultra96v2 kit from his class. He agreed, and so we will be using this board as our backup. We are still waiting for the Kria KR260 from AMD. I hope we will be given guidance on how to set up the board (and other boards in general), because I’ve been struggling to follow the online guides.
Aside from environment setup, I also worked on our RRT implementation. While we are almost done with a sparse version built on an octree, I thought of a problem with using this sparse version, and thus decided that we should have a dense version, represented simply using a 3D array/matrix. We will be implementing this in the coming week.