Last week, I performed additional verification of my UART receive_connector module as we were experiencing difficulty with comms. This revealed that my design was functioning as expected, but a few minor bugs with chip_interface were identified and corrected. Following that, I worked on getting up to speed on Jae’s work at the integration level, paying specific attention to the demo assembly program that our CPU runs. In anticipation of my upcoming presentation this week, I am generating slides and rehearsing to ensure effective timing.