With the recent events, retrieving the DE0-Nano for testing after spring break wasn’t possible. While we are able to put together some of the initial hardware, we have dedicated work to verification of the code. As such, the validation will be split into two sections:
1. RPi Ethernet packet transfer
This test is essentially the program itself. A dummy routine will replace the SPI protocol in order to verify that packets are correctly processed.
2. FPGA data transfer
The RPi is communicating through SPI bus, which is thankfully incredibly easy to mimic in verilog. A testbench will require validating both sending and receiving data across the clock domains (125 MHz from SPI, 50 MHz from the DE0-Nano).
The RPi does not need a SPI test, as an external library handles the read and write calls.
This is incredibly behind schedule, but we live in incredible times. I’ll make sure to at least get the RPi Ethernet packet transfer test working.
On a side note, I am repurposing an old desktop as a SSH server for the team. It and the Pi will have internet access. I am taking precautions for the Pi, as I am aware that having an open interface with the username “pi” is unwise.