Its time to get working on that ethernet, and with a couple shake-ups in the design there’s a new board on the radar: the DE10-Nano SoC. The DE10-Nano has an onboard ethernet PHY chip and is cheaper than the RPi/DE0-Nano setup, along with the Cyclone V chip being a generation ahead. This is possibly a major change in the bus protocol, so I’m reordering the tasks for the week ahead to focus on aspects relating to synthesization.
In terms of this week, I gave a presentation on machine learning. I don’t know anything about machine learning.
The RPi is giving me more trouble than its worth, and to connect to it I had to reformat it. So far this week I set up a simple test program for the GPIO and SPI bus via the bcm2835 library. No test on the FPGA yet, but I did get a loopback read/write to work.
This next week is dedicated to a few tasks: Deciding if the DE10-Nano SoC is fine to switch to (I’m favoring it) and writing some Verilog to test the SPI bus and obtain data. If we switch to the DE10, the code will form the implementation of the communication protocol.