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Team A0 Carnegie Mellon ECE Capstone, Spring 2019

Status Reports

Charles’ Mar 9 Status Report
Posted by : Charles Li Charles's Status Reports

Work Update

This week was spent for me mostly working on making sure that our design proposal was well laid out and making sure that the parts of it that were mine were presentable. This meant taking all of the design work I’ve done so far and combining it together into a readable format as well as continuing to explain and further flush out my ideas.

Scheduling

Due to the amount of work that I’ve had to put into overhead recently, I’ve fallen a little bit behind schedule, but expect to use Spring Break to catch back up to where I need to be.

Jens’ Mar. 9 Status Report
Posted by : jertman Jens’ Status Reports

Work Update

This week the entirity of my bandwidth for capstone for the front end of the week was consumed by writting my portion of the Design Document. This ended up taking considerably more time than was expected to complete as certain parts of the formatting did not want to play nice with inserting new figures and copying over text from Google Docs where we could colaborate as a team on the document. After the Design Document was due I had a lot of work in my other classes leading in to spring break and was completely swampped. As a result of this and the amount of time that the design document took, I was unable to complete most of the work that I had hoped to complete this week. This included writing the first pass of all of the verilog modules for the wavetable synthesis portion of the pipeline and creating the pakage file for sending translated MIDI control messages.

Scheduling

Now that I am behind schedule from the progress that I had hoped to make last week I have lost the bit of slack that I had gained from weeks prior. In addition despite the fact that this coming up week is Spring Break and I am going to be in London having fun for the duration of the week, I am going to have to try and take time out from siteseeing and watching soccer games to write the verilog files for this project. This means that for the coming up week I hope to have the first pass at the verilog files complete and have to complete the ethics case study for next weeks class as well.

Hailang’s Mar. 9 Status Report
Posted by : Hailang Liou Hailang's Status Reports

Weekly Progress

The beginning of the week was spent busy polishing up the design review report and integrating everybody’s parts together. We had all written our sections independently and consolidated in the end, since it was difficult to work on it collaboratively with the formatting. I worked on filling in extra details on some sections, and also worked on formatting the final report (formatting in Word can be a pain).

Unfortunately, I think that most of our group got caught in a slew of midterms this week which ate up a lot of our available time. We worked as a group to flesh out the interfaces between a lot of our modules this week, and we each planned out our goals on work over Spring Break.

This week, I worked more on the Verilog implementation side as well, although less than I would have liked. Implementation of both the actual modules and the testing framework is underway now and I don’t anticipate there being any major issues in terms of scheduling.

Goals for Next Week

Next week is Spring Break, and I have very little planned, so I will try to get as much of the Verilog implementation done over the break. I have a small electronics lab setup at home, so I will see if I can run some tests on both the MIDI interface components as well as try to test my personal synthesizer for benchmarking purposes. My main goal will be to finish up the implementation stage for effects and begin the testing and fine-tuning steps.

Team Mar. 2 Status Report
Posted by : Hailang Liou Team Status Reports

Changes to the Design

Since there was not too much work done over this week in order to prepare the design review presentation and paper, there are no major design changes either. Professor Mai recommended during the design review presentation that we could utilize the extra block ram to simplify the logic of the effects chain, which is something we had considered to some extent before (extra instances of the wavetable for unison effect calculations). By our rough estimate, we will probably use up a little more than half of the M10K block rams on the Cyclone V, mostly taken up by the delay FIFOs, so we would definitely have the wiggle room for this. One plan for the extra block ram was just to add more waveshapes, since each wavetable only uses up about 2 M10Ks, and it would make the synthesizer cooler to play with without requiring much work. We will further explore utilizing the extra block ram for precomputed effects throughout the next week or two however.

Risks

We do not see any changes to the risk factors from last week, and some of the worries regarding integration have been somewhat alleviated by the creation of the block diagrams for our synthesis and effects pipeline.

Schedule

We are all somewhat behind schedule due to the preparation of the design review presentations and document, but we do not see this as a major issue due to the weeks of built-in slack time within out schedule. There are no changes to the schedule to be made at this time.

Charles’ Mar. 2 Status Report
Posted by : Charles Li Charles's Status Reports

Weekly Progress

This week I focused most of my efforts on helping Jens to prepare for the presentation as he was less well-versed in the analog side of the project. I also put forth a lot of time in starting our report. This week has been spent mostly on overhead for our project to make sure that our design is in a good place before we get to spring break so that we have working ideas after spring break.

Scheduling

In terms of scheduling, I have fallen a little bit behind schedule, but I feel confident that I should catch back up due to a lot of slack built into my schedule, as well as some progress that has already been made on other parts that I have been assigned. This occurred due to planning and the connectedness of my parts that allowed me to make some progress in other areas unexpectedly.

Hailang’s Mar. 2 Status Report
Posted by : Hailang Liou Hailang's Status Reports

Weekly Progress

I didn’t get a lot of time to work on the actual meat of the project this week, since a lot of the time I had was focused on the design review presentation as well as on the design review paper. The design review presentation went very well, and I am happy with the feedback we got. Through the course of preparing the presentation and the paper, I have fleshed out the designs of the effects modules and have developed block diagrams for the effects modules, as well as working with the other group members to develop the flow of the whole effects pipeline. Thus while the actual implementation did not make much progress this week, I hope the time spent designing the effects modules will prove to save time in the implementation and debugging stages later on.

This week I also got to spend a little bit of time messing with the MIDI keyboard I received last week, and it turns out that it should work well with the project. I found a MIDI cable that has a detachable head and exposes the wires, which will help a lot when wiring together the support circuitry. Unfortunately, I am currently missing a part that I would need to create the complete circuitry, and I am waiting on the rest of the analog parts list to be fully fleshed out in order to save money on shipping ($10 shipping on a $0.80 part?). However, if the parts list needs more time, I will just place the order early this week anyways and just eat the shipping cost into the budget, as we don’t have a lot of parts we need to buy, so we should have plenty of budget to spare. In other news, I also recently purchased a nice synthesizer for fun, and for the project, we can use it as a comparison for testing purposes. Hopefully, we can get our hands on some other commercial synths in the coming weeks so we have more to test against.

Goals for Next Week

Due to us not really anticipating the amount of work that needed to go into the design review, and it not being properly allocated in the schedule, I am probably a little behind in my implementation goals for the effects modules. However, due to our built-in slack, I will be able to pick up the pace of development of the effects modules. I would like to get at least bare-bones versions of the effects modules finished by this week and begin developing a testing framework for the effects pipeline.

Jens’ Mar. 2 Status Report
Posted by : jertman Jens’ Status Reports

Weekly Progress

This week I worked on the design presentation slides, preparing for the presentation, and creating block diagrams in digi-key’s design drawing tool.  For the slides I work on all of the slides that covered aspects of my portion of the pipeline which is the digital synthesis section.  The meat of this work was in creating the overall block diagram for this section.  It was my first time using the digi-key diagram drawer and it took a little while to get used to.  However now that I know how to use it, it is a very useful tool for creating standardized block diagrams.  Additionally, I was the member of the group who gave the design presentation.  Therefore, a good amount of my attention on capstone for the first half of the week was spent preparing for the presentation.  This involved meeting with Zilei for a dry run of the presentation and running it myself multiple times.  For the latter half of the week I spent time working on the digital synthesis sections of the design document as well as portions of the validation and verification sections.

Scheduling

I am currently on schedule for this week as our schedule added in a week of time budgeted to preparing the design presentation and the design document.  My goals for next week are to tomorrow and Monday finish the design document.  Additionally, I would like to get down a skeleton of all of the Verilog files I am going to be using for the digital synthesis portion of the pipeline.  This includes a package and macros file where the types for the ports, such as note names and control knob names, will be defined for interfacing across the whole system.  This may conflict with what is currently on the schedule for me to complete for next week however because it is work that goes towards all of the parts of the pipeline I want it to be completed first so at least all of my interfaces are well designed.

Team Feb. 23 Status Report
Posted by : Hailang Liou Team Status Reports

Changes to the Design

Last week one of the large changes to the design that we were considering was the implementation of the wavetables in either the SDRAM on the FPGA or in the LUTs of the FPGA.  After design work and deliberation this week we realized that we had neglected to consider a different option of using the block RAM on the FPGA. After running a series of tests to determine how much of this block RAM would be necessary to implement the features that we wish to use memory for we decided that for the board that we are planning to use placing the wavetables in block RAM is the best solution. See Hailang’s weekly report for more details regarding these changes.

Risks

Moving forward a big risk that is becoming apparent is in underestimating the difficulty of the tasks and interfacing between different elements of the project.  For example during the more in depth design process it became clear to us that there would be an issue with interfacing the sample generation component with the effects and DAC because they operated at different clock frequencies.  This was an issue that we had thought about but not on a deep enough level to understand some of the unforeseen issues involved. The two clocks that we had intended to use were a 50 mHz system clock and a 44.1kHz clock for the effects and DAC.  However 50mHz is not evenly divisible by 44.1kHz so this would lead to issues. We believe that this can be dealt with by using the onboard PLLs to generate a system clock that is evenly divisible. However this is just an example of the integration and design consistency risk that we foresee going forward.

Schedule

Currently there have been no modifications to the schedule.

Charles’s Feb. 23 Status Report
Posted by : Charles Li Charles's Status Reports

Weekly Progress

This week I stalled out a little bit. I made a slight miscalculation in my transfer functions for my filters, which led to a lot of going backwards and recreating some of the values that I had originally. I did manage to toss together several components to start preparing for purchasing so that I can start building and testing the DAC as well as the filters that I have designed. I hope to continue to document clearly my thought processes for these designs to ensure that if I encounter any bugs in the future, I can understand why I made my errors to begin with, as that has helped me already in debugging some of my circuitry.

Additionally, I spent several hours preparing our presentation as well as the website so that they would look presentable. This includes formatting the website as well as clearly drawing out my designs in software rather than on a sheet of paper.

Scheduling

I was scheduled to start implementing some of the analog filter and DAC design this week, but I should be beginning to do this next week and I have an extra week of slack to make up for the lost week I have due to presentation overhead as well as errors that I have made.

Deliverables

By the end of this week, I hope to have my materials ordered and hopefully in, so that I can begin to build my filters and test them for accuracy.

Jens’ Feb. 23 Status Report
Posted by : jertman Jens’ Status Reports

Weekly Progress

This week I created the design documentation for my modules of the project.  These included the MIDI decoder, Polyphony Control, Wavetable Access, and the Sub-Sample Mixer.  This design documentation was taking the overall idea for what each module should do and create a more concrete understanding of what the specific behavoir of each module would be and what its inputs and outputs would be.  Additionally I took this more indepth design process and used it to make the block diagram for this phase of the digital synthesis chain.  The image of this diagram will be attached to this post.  Following this I spent a considerable amount of time working on the presentation slides and preparinghhhhhhhhhh for the design presentation this upcoming Monday, as I will be the group member giving the presentation.

Earlier in the week I worked on creating some preliminary simulations of what the output spectrum of various wavetable sizes would be using Matlab.  From these simulations it was determined that a wavetable size of as low as 256 samples per wavetable wouldnt present issues to the distortion of the end signal.  I also worked to figure out how much space in the block ram these wavetables would take up and how best to use this space.

Scheduling

This week I was scheduled to do the first half of the wavetable incrementer.  That constituted the more indepth design work that I did on the wavetable incrementer module with also includes properly generation of the two unison incrementations.  Currently the schedule is slightly off due to the nature of the project being puntuated by the overall design presentation so the actual implementation half of the wavetable incrementer will occur later.

Deliverables

In the coming week I would like to complete a second revision and overall connection of the system wide block diagram.  Additionally I would like to in the next week begin the actual verilog code for the MIDI decoder module as we have purchases a MIDI controller and now know the specific values of all of its output controls.