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Team A0 Carnegie Mellon ECE Capstone, Spring 2019

Status Reports

Jens Apr. 20 status report
Posted by : jertman Uncategorized

Progress

this week for progress I finished implementing and testing the version of the polyphony control module that works with the newly added ADSR envelope control module designed by Charles. the main change between this version of the module and the version that I had previously designed is that this version does not remove the stored value of notes that have been released until after a new note comes in to replace it.  This is because the R in ADSR stands for release and is the tailing envelope that controls the volume of the note after the key has been released.  The previous behavior would have been to free up this potential note space and make the note stop playing immediately after release.  The one major disadvantage to this new design is that the Polyphony will always hold the last 4 notes pressed even if they are no longer being held and without a working ADSR envelope module it will continue to play out these notes.

Scheduling

This progress is up to the level that was wanted in the schedule however due to modifications in other parts of the project the integration process and validation that it works properly.  That is the portion of the project that we are spending tomorrow working on in correcting and testing the analog end of the project so that it can be used for behavioral testing of the digital components we have in the synthesis pipeline.

Team April 20 Status Report
Posted by : Charles Li Team Status Reports

Progress

This week, we finished building all of our necessary modules and are currently working on integrating all of them. We intend to finish integration by tomorrow night and complete tests by the end of next week. This will allow us some time to begin our final report and presentation work.

Scheduling

In terms of scheduling, we are a little bit behind, but have made up for some of the later testing we intended to do by testing our individual modules first before integration. This has sped up the process significantly. Our biggest worry is that we will run into bugs with integration. The analog portion of our design might be difficult to integrate at the end since it is more difficult to debug. Furthermore, the untested nature of some of our modules in the overall pipeline provides some level of concern about completing our full integration.

Charles’ April 20 Status Report
Posted by : Charles Li Charles's Status Reports

Progress

This week, I managed to finish wiring up and making look somewhat nice the filters and equalizer for our sound output. Only thing left to do are a couple of tests to check that they work as expected. I also managed to write up the rest of the ADSR module and wait for integration to determine how accurate it is.

Scheduling

In terms of scheduling, I just need to do some testing and I will be effectively on track for where I intended to be. This is likely to be done before demos start on Monday.

Jens’ Apr. 13 Status Report
Posted by : jertman Jens’ Status Reports

Progress

This week for progress there was carnival so the back half of the week was less productive that I would have hoped it to be however, I did make progress on the new version of the polyphony control that supports 4 notes.  However there was a slight change to the overall design of the system with the addition of an ADSR envelope feature that Charles made progress on,  Because of this there are significant but rather simple changes that had to be made to the way that the polyphony control module worked.  Additionally there needs to be the proper support placed into the incrementation module for unison control.  This will be a percentage change from the normal value either up or down.  The module is currently assembled to support this feature however the multipliers that would perform this function have yet to be added.  However this week Hailang did find an online database of different waveshapes to use for the project.

Schedule

Because of this I am slightly behind the schedule I would like to be on with the schedule currently dictating that I would have completed the polyphony control by this point.  However because the needed alterations to the module are due to the addition of the ADSR feature I am okay with being behind schedule on this portion of the project.  Currently the biggest risk that I am facing is in the integration of the new features into the pipeline because some of them mean that multiple new modules need to be added at once as opposed to the old plan where each new module could be integrated independently.

Charles’ April 13 Status Report
Posted by : Charles Li Charles's Status Reports, Uncategorized

Progress

This week I started writing an ADSR module (another feature I picked up while waiting on parts), and I ordered my parts on Monday (Tuesday went in) and am waiting on those parts to start constructing my filters.

Scheduling

In terms of scheduling since the filter materials did not arrive on Thrusday, I’m a bit behind, but I’ve also picked up something else to be doing, so I’m still being productive and moving the project forward.

Team Apr. 13 Status Report
Posted by : Hailang Liou Team Status Reports

Progress

This week we continued to finish up the specification feature set and expand from what we had at the midterm demo. Jens is working on expanding the polyphony voices and finishing up the core synthesis pipeline, Hailang has been working on the wavetables and tuning the effects chain, and Charles has been working on adding ADSR envelopes to the synthesis pipeline while he waits for parts to arrive. We anticipate to fully integrate our feature specification next week, as Hailang and Jens will finish the synthesis pipeline and Charles can finish constructing his filters.

Scheduling

The main risk at this point in time is if the analog filter or amplification stages do not perform to specification. We have enough time to compensate and course adjust if issues arise, but it will delay finishing testing until we can isolate the issue and/or find new parts. The parts we use are all designed for audio applications though, so we do not think there will be any major issues there. All that will be left is testing and evaluation according to the metrics we had set.

Hailang’s Apr. 13 Status Report
Posted by : Hailang Liou Hailang's Status Reports

Progress

This week I worked on several things, namely wavetable controllers and effects tuning.

We realized early this week that because the delay and reverb effects would use too much block RAM on the FPGA that it was no longer viable to make multiple copies of the same wavetable for multiple accesses. At each sample, we need to get a maximum of 8 sample values from the wavetable ROM but the block RAM is only two ported. Therefore, this week, I designed, implemented, and tested wrapper modules for the wavetable that would allow us to access an arbitrary number of wavetable entries at once and get all the data in a fixed delay some cycles later. For the wavetables, I also created modules that would generate simple wave shapes like sawtooth and triangle waves without needing the actual block RAMs.

On the effects end, I finished the design and implementation of the effects chain and have begun tuning. I wrote a Python script that would simulate the reverb module and allow me to quickly iterate through reverb parameter values in software to see what sounded good. I have found a set of parameters that sound good enough for now, although it’s not perfect and I may revisit reverb tuning later. I have also been running comparison tests in both Audacity and MATLAB to get a subjective comparison of what software reverb algorithms.

I have also worked on consolidating segments of the pipeline into a module hierarchy, because I want to try adding a simple recording+looping functionality that would be simple if the correct pieces of the synthesis pipeline are collected in a module that I can black-box and reuse. The main constraint of the recording and looping function is again the availability of block RAM on the device, although with the new wavetable wrappers and the revised reverb design, we should have enough block RAM to spare.

Scheduling

I am satisfied by the progress made this week and believe I am still on track overall for the endgame. My goal this week is to put the whole effects chain on the board and test on real hardware, although part of this is contingent on the analog parts arriving and the amplifier stage being finished.

Jens’ Apr. 6 Status Report
Posted by : jertman Jens’ Status Reports

Progress

So far this week was a rather productive week for my work on the project.  To begin with I helped the group finish the version of the project that would be viable for the midterm demonstration demo.  This involved adding the last of my two modules for this stage of the project to the pipeline.  Those included the wave table sample fetching portion and the mixing of all of the samples that had been fetched.  Next after the midpoint demo which we feel went rather well I worked on getting adding a few of the features that are necessary for moving the project from where it is right now to its final stage.  This included most importantly adding the ability to play multiple notes at the same time.  This affected primarily one area of the pipeline and that is the note control module.  The reason that this is a difficult task to implement is that it involves remembering the order that keys were pressed down in and properly updating that order should a key be lifted in a different order than the order it was put down.  Furthermore a few more wavetable shapes are looking to be added to the project.  These include a square wave and a sawtooth wave.  Once these two waveshapes are confirmed to be working we will begin to add other shapes such as ones with specific harmonics stressed and a few random ones.  Additionally I derived a symbolic equation for determining the incremental value of the base note of each note.  This is useful because I can supply it to Hailang so that he can make the incrementation module be parameterized to be independent of the actual frequency that the system is running on.

Scheduling

According to the new schedule that was created as part of the interim midpoint demo I am still on track for the work that needed to be completed.  The only issue is that one of the weeks for doing work coming up is Carnival which hopefully will not conflict too heavily with progress on the project.

Team Apr. 6 Status Report
Posted by : Hailang Liou Team Status Reports

Progress

This week, we finished up integration and integration testing and completed the end-to-end flow of the synthesizer, such that pressing a key on the keyboard will create sounds on the analog end. Based on preliminary results from our midterm demo product, we are working on a redesign of some parts of the analog filter stage and are also on developing the final amplifier stage to work smoothly with the speaker. On the digital side, we are working on expanding the demo product to include effects and full polyphony, as well as investigating the possibility of needing a digital filter stage.

Scheduling and Risks

We are currently on schedule and do not believe there to be any significant risk ahead. The possibility of needing the final digital filter stage presents some amount of uncertainty, but the main consequence of failing to have the filter ready by the end means some larger amounts of distortion at the very high frequency (highest octave). Fortunately, we believe the difficulty in the filter implementation is low given the filter itself can be configured as an IP core and the filter parameters generated in MATLAB.

Hailang’s Apr. 6 Status Report
Posted by : Hailang Liou Hailang's Status Reports

Progress

Early this week, we had finished integrating the end-to end flow and was able to get sounds playing from keypresses on the keyboard. Later on in the week, I spent some time working on miscellaneous additions to the project that were not detailed in the schedule such as integrating the control knobs into the synthesis pipeline. I also spent a decent amount of time cleaning up the code and removing artifacts from demo-preparation.  I have begun investigating the necessity and implementation of a digital low-pass filter stage before the DAC stage and have played around in MATLAB for filter parameter generation, as well as investigating the digital filter IP cores available for our FPGA. Finally, I resumed work on the effects chain, working on beginning to integrate the effects into the current synthesis chain

Scheduling

I am on track given the revised schedule we developed at the midterm demo. Next week I will work on tuning effects parameters and will begin either working on other parts of the synthesizer or start working on testing. I will need to run more experiments once we have a finished analog filter stage to see whether or not some of the high frequency distortion is caused by the lack of a proper amplifier stage or if the digital filter stage will be necessary. I have a lot of confidence in where we stand as a group after the integration testing we ran last week.