Category: Jens’ Status Reports

Progress

For this week I worked on helping with the final polish and integration of the system which included mostly soldering the filters onto protoboards and testing to make sure that they retained their functionality.  The hope was that this more secure system would cut down on noise we heard when wires on the breadboard were touched and wiggled around.  This will hopefully be the last step in getting the project all prepared and ready for presentation at the final demo.  Moving forward to next week there is still the final changes to the paper that need to be made for the final paper and my part is rewriting the technical details of my polyphony process as it has changed from the design review to support the ADSR feature.  Also we need to film the demo version for the video.

Scheduling

At this point the schedule is what it is.  Work has been done and there are a few tasks left and one day left to do them so anything not currently ready will be finished tomorrow.

Progress

This week for progress there was carnival so the back half of the week was less productive that I would have hoped it to be however, I did make progress on the new version of the polyphony control that supports 4 notes.  However there was a slight change to the overall design of the system with the addition of an ADSR envelope feature that Charles made progress on,  Because of this there are significant but rather simple changes that had to be made to the way that the polyphony control module worked.  Additionally there needs to be the proper support placed into the incrementation module for unison control.  This will be a percentage change from the normal value either up or down.  The module is currently assembled to support this feature however the multipliers that would perform this function have yet to be added.  However this week Hailang did find an online database of different waveshapes to use for the project.

Schedule

Because of this I am slightly behind the schedule I would like to be on with the schedule currently dictating that I would have completed the polyphony control by this point.  However because the needed alterations to the module are due to the addition of the ADSR feature I am okay with being behind schedule on this portion of the project.  Currently the biggest risk that I am facing is in the integration of the new features into the pipeline because some of them mean that multiple new modules need to be added at once as opposed to the old plan where each new module could be integrated independently.

Progress

So far this week was a rather productive week for my work on the project.  To begin with I helped the group finish the version of the project that would be viable for the midterm demonstration demo.  This involved adding the last of my two modules for this stage of the project to the pipeline.  Those included the wave table sample fetching portion and the mixing of all of the samples that had been fetched.  Next after the midpoint demo which we feel went rather well I worked on getting adding a few of the features that are necessary for moving the project from where it is right now to its final stage.  This included most importantly adding the ability to play multiple notes at the same time.  This affected primarily one area of the pipeline and that is the note control module.  The reason that this is a difficult task to implement is that it involves remembering the order that keys were pressed down in and properly updating that order should a key be lifted in a different order than the order it was put down.  Furthermore a few more wavetable shapes are looking to be added to the project.  These include a square wave and a sawtooth wave.  Once these two waveshapes are confirmed to be working we will begin to add other shapes such as ones with specific harmonics stressed and a few random ones.  Additionally I derived a symbolic equation for determining the incremental value of the base note of each note.  This is useful because I can supply it to Hailang so that he can make the incrementation module be parameterized to be independent of the actual frequency that the system is running on.

Scheduling

According to the new schedule that was created as part of the interim midpoint demo I am still on track for the work that needed to be completed.  The only issue is that one of the weeks for doing work coming up is Carnival which hopefully will not conflict too heavily with progress on the project.

Progress

This week I worked on integrating the modules that I had designed with the rest of the system and actually putting them onto the FPGA.  Currently as it stands the components through the wave tables have been connected to the system and have been tested to work with the MIDI messages that we can now read on the FPGA.  Additionally I helped Charles a little with the other end of the circuit getting the filters constructed and tested and getting a signal to pass through the DAC and be converted to analog.  Moving forward from here we hope to have a MIDI controlled sound driven through the system in time for the midterm demo.

Scheduling

According to the new version of the schedule we are now decently back on track with the coming weeks being fine tuning of the system and addition of the new components for the final iteration

Progress

This week for the project I worked on getting a functioning version of the digital synthesis pipeline working.  This version of the pipeline involved a scaled back synthesis engine from the one that will be implemented for the final project.  Where the final version will support 4 note polyphony the goal for this first version is to have a single note be detected decided and the proper samples fetched and sent to the DAC.  For the most part this just simplifies the path to focus on one sample being fetched at a time instead of 4. This is then rather simple to scale back up to 4 notes once working. The one area where the scaling to multiple notes is less simple is in the logic that remembers which notes are being played at a given time and decides which note to throw away should an extra note be played.  This will be the focus of my work going forward, getting this module to function in the way that we want it to. In initial designs the difficulty was in keeping track of the priority of which note to be replaced, and specifically updating priority for the notes still being held once a note is released.

Scheduling

Moving forward with scheduling it is much more tight than I would have liked it to be.  There is still slack at the end of the semester to run into but at the moment I am behind schedule.  Once the midterm demo version of the project is complete I am going to ask the other group members if they are on track and if they can pick up some of the work on the mixer portion of the synthesis chain.  Hopefully this will help to get my allotted portion of the project back on task.

Work Update

This week the entirity of my bandwidth for capstone for the front end of the week was consumed by writting my portion of the Design Document. This ended up taking considerably more time than was expected to complete as certain parts of the formatting did not want to play nice with inserting new figures and copying over text from Google Docs where we could colaborate as a team on the document. After the Design Document was due I had a lot of work in my other classes leading in to spring break and was completely swampped. As a result of this and the amount of time that the design document took, I was unable to complete most of the work that I had hoped to complete this week. This included writing the first pass of all of the verilog modules for the wavetable synthesis portion of the pipeline and creating the pakage file for sending translated MIDI control messages.

Scheduling

Now that I am behind schedule from the progress that I had hoped to make last week I have lost the bit of slack that I had gained from weeks prior. In addition despite the fact that this coming up week is Spring Break and I am going to be in London having fun for the duration of the week, I am going to have to try and take time out from siteseeing and watching soccer games to write the verilog files for this project. This means that for the coming up week I hope to have the first pass at the verilog files complete and have to complete the ethics case study for next weeks class as well.

Weekly Progress

This week I worked on the design presentation slides, preparing for the presentation, and creating block diagrams in digi-key’s design drawing tool.  For the slides I work on all of the slides that covered aspects of my portion of the pipeline which is the digital synthesis section.  The meat of this work was in creating the overall block diagram for this section.  It was my first time using the digi-key diagram drawer and it took a little while to get used to.  However now that I know how to use it, it is a very useful tool for creating standardized block diagrams.  Additionally, I was the member of the group who gave the design presentation.  Therefore, a good amount of my attention on capstone for the first half of the week was spent preparing for the presentation.  This involved meeting with Zilei for a dry run of the presentation and running it myself multiple times.  For the latter half of the week I spent time working on the digital synthesis sections of the design document as well as portions of the validation and verification sections.

Scheduling

I am currently on schedule for this week as our schedule added in a week of time budgeted to preparing the design presentation and the design document.  My goals for next week are to tomorrow and Monday finish the design document.  Additionally, I would like to get down a skeleton of all of the Verilog files I am going to be using for the digital synthesis portion of the pipeline.  This includes a package and macros file where the types for the ports, such as note names and control knob names, will be defined for interfacing across the whole system.  This may conflict with what is currently on the schedule for me to complete for next week however because it is work that goes towards all of the parts of the pipeline I want it to be completed first so at least all of my interfaces are well designed.

Weekly Progress

This week I created the design documentation for my modules of the project.  These included the MIDI decoder, Polyphony Control, Wavetable Access, and the Sub-Sample Mixer.  This design documentation was taking the overall idea for what each module should do and create a more concrete understanding of what the specific behavoir of each module would be and what its inputs and outputs would be.  Additionally I took this more indepth design process and used it to make the block diagram for this phase of the digital synthesis chain.  The image of this diagram will be attached to this post.  Following this I spent a considerable amount of time working on the presentation slides and preparinghhhhhhhhhh for the design presentation this upcoming Monday, as I will be the group member giving the presentation.

Earlier in the week I worked on creating some preliminary simulations of what the output spectrum of various wavetable sizes would be using Matlab.  From these simulations it was determined that a wavetable size of as low as 256 samples per wavetable wouldnt present issues to the distortion of the end signal.  I also worked to figure out how much space in the block ram these wavetables would take up and how best to use this space.

Scheduling

This week I was scheduled to do the first half of the wavetable incrementer.  That constituted the more indepth design work that I did on the wavetable incrementer module with also includes properly generation of the two unison incrementations.  Currently the schedule is slightly off due to the nature of the project being puntuated by the overall design presentation so the actual implementation half of the wavetable incrementer will occur later.

Deliverables

In the coming week I would like to complete a second revision and overall connection of the system wide block diagram.  Additionally I would like to in the next week begin the actual verilog code for the MIDI decoder module as we have purchases a MIDI controller and now know the specific values of all of its output controls.