This week, we have started diving deep into the design of the project. I worked mostly on the design of the MIDI – FPGA interface, but I also spent a considerable amount of time helping design the wavetables, something not in my schedule.
I researched the MIDI specification and determined the best way to connect the keyboard to the FPGA. While most modern MIDI keyboards send messages over USB, I ultimately concluded that time spent designing a USB controller or fiddling with a USB IP block would not be the most productive use of time and decided that the alternate serial MIDI connection would be better suited for the project. Unfortunately, running with the serial connection has significant downsides. First, the serial connection runs at only 31k baud, which means a full MIDI message will take almost 1ms to send. Second, the MIDI spec requires some analog support circuitry on the receiving end, before the signal can be received by the FPGA. There are examples of such circuitry for use with Arduinos online, but we will need to run tests and tweak the circuitry to work with the FPGA. Finally, not all MIDI keyboards have a serial out and I have spent some time looking for a suitable keyboard online that is both cheap and includes enough knobs to control the effects. My aim is to make the purchase order by Monday. Fortunately, the message will be sent over UART, which will be fairly simple to implement in Verilog, which I have begun doing.
On the wavetable side, we have been discussing within the team what way would be best to store the wavetables. Ideally, the wavetable would have enough samples to minimize interpolation, but having at least 4 wave shapes means the memory usage of the tables can grow to be quite large. We have been discussing and researching several options: putting it on the SDRAM (8MB available), putting it on the flash memory (4MB), or putting it in LUTs on the FPGA itself (15k LUTs total). For the SDRAM and flash memory, we would have to either find a memory controller or write one from scratch, with the SDRAM also having the additional requirement of reloading the tables onto the board every power-on. We would vastly prefer not to write one from scratch, but we are still unsure about whether we will be able to find a suitable memory controller elsewhere. I have been researching options and have been looking for memory controllers given by the FPGA board maker, and have possibly found one that could work. More details about this debate can be found in the team report.
I am a little behind schedule since I had wanted the whole interface to be near completion by the end of the week, but I think after overcoming the design problems that I fleshed out this week, implementation will be straightforward. Next week on the schedule is built in slack for me, so I don’t need to take any special actions to catch up in my opinion.
For next week, I want to have be able to have the interface fully implemented and tested. I am unsure about whether I can get the MIDI keyboard shipped here by the end of the week, so I was planning on using Jens’s keyboard to test the circuit and UART receiver. I also want to run some experiments about wavetable sizes in Quartus and conclusively decide on what way to store the wavetables in the board.