Category: Hailang’s Status Reports

Progress

This week is the last week of work, and has been spent on getting things ready for the final demo.

For the actual synthesizer, I spent this week debugging several issues with the DAC module, did some last minute tuning of effects, and worked on the extra looping feature that we can hopefully have by Monday.

For the DAC, we realized that one of the big sources of noise in our system was incorrect samples coming out of the physical DAC chip, and after many hours of debugging, we realized that the timing of our DAC module on the FPGA may be violating the required setup tim internal to the DAC. Further debugging also revealed that occasionally the sample would change partway through the serial data transmission, leading to completely wrong samples being fed into the DAC. Finally, the very last bug was that we found out that the sine wavetable was missing a sample entry, leading to audible periodic noise. Now there is very little noise audible, which makes me very happy.

For the wavetables, I finished writing a Python script that would transform .wav files into MIF files of the correct format and sample rate to work with our synthesizer. For the complex waveforms, we found a very extensive database of complex wavetables online, and we chose our 4 favorite ones to use in the synthesizer.

For effects, I did some last minute tuning to a lot of the effects, tweaking parameters used in the reverb and unison, as well as adding a phase difference effect in the wavetable blending, which will hopefully improve the blending effect by adding another parameter.

I continued work on the looping module, though I am unsure whether it can be tested and ready by Monday. A lot of my time this week that I had hoped to spend on looping

Finally, I spent a lot of time this week working on the final presentation and poster.

Hopefully everything can be wrapped up in the next day, and we’ll have a good demo. All the noise is gone now, so its just polishing from here on out. I feel pretty good about where we stand now, since my biggest worry was that we couldn’t get rid of the noise and that issue is solved.

Progress

This week was spent mostly on debugging, testing, and preparing for the final in-lab demo and presentation.

For debugging, I worked with the team on integrating all the parts into the final product. The digital side of things is essentially feature complete (with a few extra features thrown in), and work on the digital side has been focused on just small tweaks and polish. Most of the debugging that took place this week was in the analog space, where we have been running into noise issues distorting the final sound quality. Wave-shape distortion issues were fixed when we swapped out the passive speakers we were originally using with powered speakers, and a lot of the noise issue was alleviated with filters in specific points of the analog pipeline. We are currently still working on fixing a ground noise issue.

Testing was done this week of many of the metrics that we set out to meet. For example, I worked on isolating and fixing a bug in the RTL that made the notes slightly flat. Much of the testing was done on the analog attributes, such as testing the filter bands to make sure they were right and testing distortion. Unfortunately, distortion metrics are being affected by the ground noise issue currently so we are still working on fixing that.

I have also begun work on the final presentation and poster, but most of that will be occurring tomorrow.

Scheduling

There isn’t much else to schedule at this point. We mainly want to flesh out the last few bugs from the analog circuitry and make sure everything sounds nice for the public demo day. I might write a few extra features on the digital side in the next week as a fun add-on.

Progress

This week I primarily worked on integration of all the components and modules. I finished the effects chain and worked on dropping it into the pipeline, as well as worked on integrating other miscellaneous components, such as making sure the knob controls worked, as well as finishing the integration of the wavetable wrappers. Most of my time was spent on integration and debugging of the full end-to-end. Time was also spent debugging the implementation and integration of the ADSR and new polyphony modules.

Scheduling

Things are still on track for demo on Monday/Wednesday, the full end-to-end with enhanced polyphony and effects should be ready by then. Next week should be spent mostly on polish as well as presentation readiness.

Progress

This week I worked on several things, namely wavetable controllers and effects tuning.

We realized early this week that because the delay and reverb effects would use too much block RAM on the FPGA that it was no longer viable to make multiple copies of the same wavetable for multiple accesses. At each sample, we need to get a maximum of 8 sample values from the wavetable ROM but the block RAM is only two ported. Therefore, this week, I designed, implemented, and tested wrapper modules for the wavetable that would allow us to access an arbitrary number of wavetable entries at once and get all the data in a fixed delay some cycles later. For the wavetables, I also created modules that would generate simple wave shapes like sawtooth and triangle waves without needing the actual block RAMs.

On the effects end, I finished the design and implementation of the effects chain and have begun tuning. I wrote a Python script that would simulate the reverb module and allow me to quickly iterate through reverb parameter values in software to see what sounded good. I have found a set of parameters that sound good enough for now, although it’s not perfect and I may revisit reverb tuning later. I have also been running comparison tests in both Audacity and MATLAB to get a subjective comparison of what software reverb algorithms.

I have also worked on consolidating segments of the pipeline into a module hierarchy, because I want to try adding a simple recording+looping functionality that would be simple if the correct pieces of the synthesis pipeline are collected in a module that I can black-box and reuse. The main constraint of the recording and looping function is again the availability of block RAM on the device, although with the new wavetable wrappers and the revised reverb design, we should have enough block RAM to spare.

Scheduling

I am satisfied by the progress made this week and believe I am still on track overall for the endgame. My goal this week is to put the whole effects chain on the board and test on real hardware, although part of this is contingent on the analog parts arriving and the amplifier stage being finished.

Progress

Early this week, we had finished integrating the end-to end flow and was able to get sounds playing from keypresses on the keyboard. Later on in the week, I spent some time working on miscellaneous additions to the project that were not detailed in the schedule such as integrating the control knobs into the synthesis pipeline. I also spent a decent amount of time cleaning up the code and removing artifacts from demo-preparation.  I have begun investigating the necessity and implementation of a digital low-pass filter stage before the DAC stage and have played around in MATLAB for filter parameter generation, as well as investigating the digital filter IP cores available for our FPGA. Finally, I resumed work on the effects chain, working on beginning to integrate the effects into the current synthesis chain

Scheduling

I am on track given the revised schedule we developed at the midterm demo. Next week I will work on tuning effects parameters and will begin either working on other parts of the synthesizer or start working on testing. I will need to run more experiments once we have a finished analog filter stage to see whether or not some of the high frequency distortion is caused by the lack of a proper amplifier stage or if the digital filter stage will be necessary. I have a lot of confidence in where we stand as a group after the integration testing we ran last week.

Progress

This week we worked together a lot on preparing for the midterm demo. We worked heavily on integration and testing, and have put together many of the pieces that we had together on hardware. The MIDI interface has been pieced together and completed, fully tested on the FPGA hardware itself. We have been testing by putting successive pieces of the pipeline together, and as of the time of writing this, we have tested the synthesis pipeline up to the decoder and synthesis incrementors, and are working on testing the mixer and the DAC pre-prep modules. We do not anticipate having the effects chain tested on the FPGA board itself for the midterm demo, and have been focusing on the wave blending effects in testing this week. The group as a whole has been working together, so rather than a lot of focus on each of our individual pieces, we have been debugging and testing together.

One issue that has come up this week is the possibility that we may need a digital low-pass filter on-board the FPGA before the DAC due to potential aliasing effects. We will run experiments on the DAC output this week to see if the issue necessitates it, and if it is necessary, I will begin the design of the filter.

Scheduling

The amount of progress we made this week on integration and testing means we will not have to spend as much time later, since the stages of the synthesis pipeline that we have working after this week will not need to be revisited later. My goals for next week are to begin integrating the effects modules and effects chain into the synthesized hardware pipeline. Assuming we can get the basic synthesis pipeline functional early next week, I can begin tuning the effects as well.

Progress

This week I worked on finishing up the first versions of effects modules. At this point, the distortion module is essentially completed, while the delay and reverb modules should be finished up this weekend. These first versions will have the necessary functionality, but are not tweaked for sounds, which is something that will be worked on in the upcoming weeks. Unfortunately, I cannot really test the effects in real life until the rest of the synthesis pipeline is in, however, I may consider using Matlab to run some simulations to fine-tune some of the effects parameters.

Realizing that the midterm demo is soon upon us, I have also spent a lot of this week revisiting the MIDI interface and decoder parts of the pipeline, since that will be critical for the midterm demo. The parts I need for the MIDI interface were obtained this week and after some simulation testing of the interface this past week, it should just be a matter of putting the pieces together.

Scheduling

While I was able to work over Spring Break, I did not end up having as much time as I anticipated, thus I am not as far as I would like to be. The goal right now is to be in a presentable state for the midterm demo, which I think will be alright, and I am potentially going to be taking over some parts of the synthesis pipeline from Jens in order to get the core of those modules absolutely nailed down. Next week, we will be spending a lot of time doing integration and integration testing, but hopefully, any issues we iron out next week will be mean that integration later will be trivial, as only the internals of the modules should change and not the interfaces between them. For the effects and such, I will begin functional testing, but tweaking and fine-tuning will likely wait until the week after.

Weekly Progress

The beginning of the week was spent busy polishing up the design review report and integrating everybody’s parts together. We had all written our sections independently and consolidated in the end, since it was difficult to work on it collaboratively with the formatting. I worked on filling in extra details on some sections, and also worked on formatting the final report (formatting in Word can be a pain).

Unfortunately, I think that most of our group got caught in a slew of midterms this week which ate up a lot of our available time. We worked as a group to flesh out the interfaces between a lot of our modules this week, and we each planned out our goals on work over Spring Break.

This week, I worked more on the Verilog implementation side as well, although less than I would have liked. Implementation of both the actual modules and the testing framework is underway now and I don’t anticipate there being any major issues in terms of scheduling.

Goals for Next Week

Next week is Spring Break, and I have very little planned, so I will try to get as much of the Verilog implementation done over the break. I have a small electronics lab setup at home, so I will see if I can run some tests on both the MIDI interface components as well as try to test my personal synthesizer for benchmarking purposes. My main goal will be to finish up the implementation stage for effects and begin the testing and fine-tuning steps.

Weekly Progress

I didn’t get a lot of time to work on the actual meat of the project this week, since a lot of the time I had was focused on the design review presentation as well as on the design review paper. The design review presentation went very well, and I am happy with the feedback we got. Through the course of preparing the presentation and the paper, I have fleshed out the designs of the effects modules and have developed block diagrams for the effects modules, as well as working with the other group members to develop the flow of the whole effects pipeline. Thus while the actual implementation did not make much progress this week, I hope the time spent designing the effects modules will prove to save time in the implementation and debugging stages later on.

This week I also got to spend a little bit of time messing with the MIDI keyboard I received last week, and it turns out that it should work well with the project. I found a MIDI cable that has a detachable head and exposes the wires, which will help a lot when wiring together the support circuitry. Unfortunately, I am currently missing a part that I would need to create the complete circuitry, and I am waiting on the rest of the analog parts list to be fully fleshed out in order to save money on shipping ($10 shipping on a $0.80 part?). However, if the parts list needs more time, I will just place the order early this week anyways and just eat the shipping cost into the budget, as we don’t have a lot of parts we need to buy, so we should have plenty of budget to spare. In other news, I also recently purchased a nice synthesizer for fun, and for the project, we can use it as a comparison for testing purposes. Hopefully, we can get our hands on some other commercial synths in the coming weeks so we have more to test against.

Goals for Next Week

Due to us not really anticipating the amount of work that needed to go into the design review, and it not being properly allocated in the schedule, I am probably a little behind in my implementation goals for the effects modules. However, due to our built-in slack, I will be able to pick up the pace of development of the effects modules. I would like to get at least bare-bones versions of the effects modules finished by this week and begin developing a testing framework for the effects pipeline.

I spent a lot of this week doing experiments with FPGA usage and deciding the best way to design both the wavetable and the delay/reverb modules. In this status report, I will describe the experimentation done, the process this week of designing some of the effects modules, and some miscellaneous items as well.

Wavetable Experiments

I started out the week working on wavetable size experiments, something I wanted to get done as early as possible (as mentioned in last week’s report). Since we wanted to avoid putting the wavetables on a memory external to the actual FPGA chip, such as SDRAM or flash, I wanted to see what the FPGA usage would be if I just put all the wavetables in the FPGA LUTs themselves and create a big combinational lookup table to act as the wavetables. Jens generated a 12-bit, 512 sample sine wave to test this idea with, and the results were a lot better than I thought! It turns out, a single one of these tables uses about 3% of the available LUTs on the smallest Terasic DE0 board (Cyclone III) used by the old iterations of 18-341. I tested with additional tables present, and the number of LUTs used scales linearly. In general, it seemed that the usage was approximately 1 LUT per 12-bit sample. However, I was recommended by Prof. Mai and Ford Seidel to explore using the FPGA’s block ram for wavetable storage instead and it seems like this will be a good solution as well. One big advantage of using the block ram is that the Quartus generated block ram modules are two ported, which will make Jens’s life a lot easier down the line when he makes the wavetable access modules. However, one downside that worries me is that using the block ram will make our design board dependent, since different boards will all have different amounts and types of block ram. While this isn’t a major problem, I had wished the design could be as portable as possible. We don’t anticipate needing to do a radical board change and any board changes will be all in the same Altera Cyclone family.

Reverb and Delay Design

I also started designing the reverb and delay modules this week. The two effects are very closely related at first glance, but are actually quite different in the nitty-gritty. Both involve creating a delay queue where the samples will pop out some number of cycles after the sample is played normally, however the queue for the reverb module will feed back into itself after being attenuated to create an echoey effect and will also be shorter than the queue for delay. Unfortunately, since the sample rate for standard audio is 44.1kHz, we will need to queue up 44,100 16-bit samples in order to create a one second delay. As with the wavetable experiments, I tried to create a quick prototype module in Quartus to see the FPGA usage of a naive implementation of the queue, but it ended up being completely crazy and infeasible (also learning that Quartus will only allow a generate loop to go 5000 iterations before dying). A 16-bit sample queue with a queue depth of only 4096 elements alone will take up 65k logic elements on a board, almost 5 times the amount on the Terasic DE0, and this queue is only big enough for less than a 100ms delay! I was again worried that I would have to deal with the on-board SDRAM and would need to hack up a controller, but luckily, it seems like block ram will come to the rescue again. The Quartus Megafunction wizard will let you synthesize a FIFO structure on block ram, which was awesome to find out, but unfortunately, a 16-bit FIFO of length 2¹⁶, a queue depth that would allow for a maximum delay of a bit less than one second, would take up 64 M9k block rams, whereas the DE0 board only has 56 such block rams. I don’t see an alternative path to implementing delay with any reasonable maximum delay, so this will probably force us to switch from the DE0. Luckily, we already had plans in place to switch to the Terasic DE0-CV, an updated board that is almost identical except for using the Cyclone V FPGA instead of a Cyclone III. The new FPGA has 308 M10k block rams, about 6 times the amount as the old board, while only being a little more expensive as to not increase the total project cost by too much. This has the added benefit of allowing us more block rams to add more wave shapes later on, something that will not take a lot of time or be too difficult, while make the user experience of the synth significantly cooler. In addition to nailing the exact implementation of the queues for the delay and reverb effects, I also got around to designing the other parts of the effect.

Miscellaneous

Finally some other miscellaneous updates. I put in the purchase order for the MIDI keyboard on Monday after lots of agonizing over it being the first purchase of the project and received the keyboard on Thursday. Unfortunately I don’t really have a good place to put it yet so it’s being hidden in the capstone lab. I plan on running some tests with the keyboard, and try interfacing it with the FPGA early next week. A lot of time this week was spent working on the presentation and documentation rather than on implementation, but I’m not too worried since a lot of the planning for future steps was hashed out this week as well. Running the tests helped lock in a lot of important design considerations for the modules that needed to be done, so overall things are running pretty smoothly.

Goals for Next Week

For next week, I aim to finish the complete design of the reverb and delay modules, and hopefully have a Verilog description mostly or completely written. I want to start testing the MIDI interface between the keyboard and the board as well. Since the comprehensive design review report needs to be done next week as well, I will not expect all of these goals to be achieved but I expect them to all be well underway.