Author: jertman

Weekly Progress

This week I worked on the design presentation slides, preparing for the presentation, and creating block diagrams in digi-key’s design drawing tool.  For the slides I work on all of the slides that covered aspects of my portion of the pipeline which is the digital synthesis section.  The meat of this work was in creating the overall block diagram for this section.  It was my first time using the digi-key diagram drawer and it took a little while to get used to.  However now that I know how to use it, it is a very useful tool for creating standardized block diagrams.  Additionally, I was the member of the group who gave the design presentation.  Therefore, a good amount of my attention on capstone for the first half of the week was spent preparing for the presentation.  This involved meeting with Zilei for a dry run of the presentation and running it myself multiple times.  For the latter half of the week I spent time working on the digital synthesis sections of the design document as well as portions of the validation and verification sections.

Scheduling

I am currently on schedule for this week as our schedule added in a week of time budgeted to preparing the design presentation and the design document.  My goals for next week are to tomorrow and Monday finish the design document.  Additionally, I would like to get down a skeleton of all of the Verilog files I am going to be using for the digital synthesis portion of the pipeline.  This includes a package and macros file where the types for the ports, such as note names and control knob names, will be defined for interfacing across the whole system.  This may conflict with what is currently on the schedule for me to complete for next week however because it is work that goes towards all of the parts of the pipeline I want it to be completed first so at least all of my interfaces are well designed.

Weekly Progress

This week I created the design documentation for my modules of the project.  These included the MIDI decoder, Polyphony Control, Wavetable Access, and the Sub-Sample Mixer.  This design documentation was taking the overall idea for what each module should do and create a more concrete understanding of what the specific behavoir of each module would be and what its inputs and outputs would be.  Additionally I took this more indepth design process and used it to make the block diagram for this phase of the digital synthesis chain.  The image of this diagram will be attached to this post.  Following this I spent a considerable amount of time working on the presentation slides and preparinghhhhhhhhhh for the design presentation this upcoming Monday, as I will be the group member giving the presentation.

Earlier in the week I worked on creating some preliminary simulations of what the output spectrum of various wavetable sizes would be using Matlab.  From these simulations it was determined that a wavetable size of as low as 256 samples per wavetable wouldnt present issues to the distortion of the end signal.  I also worked to figure out how much space in the block ram these wavetables would take up and how best to use this space.

Scheduling

This week I was scheduled to do the first half of the wavetable incrementer.  That constituted the more indepth design work that I did on the wavetable incrementer module with also includes properly generation of the two unison incrementations.  Currently the schedule is slightly off due to the nature of the project being puntuated by the overall design presentation so the actual implementation half of the wavetable incrementer will occur later.

Deliverables

In the coming week I would like to complete a second revision and overall connection of the system wide block diagram.  Additionally I would like to in the next week begin the actual verilog code for the MIDI decoder module as we have purchases a MIDI controller and now know the specific values of all of its output controls.