Author: jertman

Jens’ May 4 Status Report

Progress

For this week I worked on helping with the final polish and integration of the system which included mostly soldering the filters onto protoboards and testing to make sure that they retained their functionality.  The hope was that this more secure system would cut down on noise we heard when wires on the breadboard were touched and wiggled around.  This will hopefully be the last step in getting the project all prepared and ready for presentation at the final demo.  Moving forward to next week there is still the final changes to the paper that need to be made for the final paper and my part is rewriting the technical details of my polyphony process as it has changed from the design review to support the ADSR feature.  Also we need to film the demo version for the video.

Scheduling

At this point the schedule is what it is.  Work has been done and there are a few tasks left and one day left to do them so anything not currently ready will be finished tomorrow.

Jens Apr. 20 status report

Progress

this week for progress I finished implementing and testing the version of the polyphony control module that works with the newly added ADSR envelope control module designed by Charles. the main change between this version of the module and the version that I had previously designed is that this version does not remove the stored value of notes that have been released until after a new note comes in to replace it.  This is because the R in ADSR stands for release and is the tailing envelope that controls the volume of the note after the key has been released.  The previous behavior would have been to free up this potential note space and make the note stop playing immediately after release.  The one major disadvantage to this new design is that the Polyphony will always hold the last 4 notes pressed even if they are no longer being held and without a working ADSR envelope module it will continue to play out these notes.

Scheduling

This progress is up to the level that was wanted in the schedule however due to modifications in other parts of the project the integration process and validation that it works properly.  That is the portion of the project that we are spending tomorrow working on in correcting and testing the analog end of the project so that it can be used for behavioral testing of the digital components we have in the synthesis pipeline.

Jens’ Apr. 13 Status Report

Progress

This week for progress there was carnival so the back half of the week was less productive that I would have hoped it to be however, I did make progress on the new version of the polyphony control that supports 4 notes.  However there was a slight change to the overall design of the system with the addition of an ADSR envelope feature that Charles made progress on,  Because of this there are significant but rather simple changes that had to be made to the way that the polyphony control module worked.  Additionally there needs to be the proper support placed into the incrementation module for unison control.  This will be a percentage change from the normal value either up or down.  The module is currently assembled to support this feature however the multipliers that would perform this function have yet to be added.  However this week Hailang did find an online database of different waveshapes to use for the project.

Schedule

Because of this I am slightly behind the schedule I would like to be on with the schedule currently dictating that I would have completed the polyphony control by this point.  However because the needed alterations to the module are due to the addition of the ADSR feature I am okay with being behind schedule on this portion of the project.  Currently the biggest risk that I am facing is in the integration of the new features into the pipeline because some of them mean that multiple new modules need to be added at once as opposed to the old plan where each new module could be integrated independently.

Jens’ Apr. 6 Status Report

Progress

So far this week was a rather productive week for my work on the project.  To begin with I helped the group finish the version of the project that would be viable for the midterm demonstration demo.  This involved adding the last of my two modules for this stage of the project to the pipeline.  Those included the wave table sample fetching portion and the mixing of all of the samples that had been fetched.  Next after the midpoint demo which we feel went rather well I worked on getting adding a few of the features that are necessary for moving the project from where it is right now to its final stage.  This included most importantly adding the ability to play multiple notes at the same time.  This affected primarily one area of the pipeline and that is the note control module.  The reason that this is a difficult task to implement is that it involves remembering the order that keys were pressed down in and properly updating that order should a key be lifted in a different order than the order it was put down.  Furthermore a few more wavetable shapes are looking to be added to the project.  These include a square wave and a sawtooth wave.  Once these two waveshapes are confirmed to be working we will begin to add other shapes such as ones with specific harmonics stressed and a few random ones.  Additionally I derived a symbolic equation for determining the incremental value of the base note of each note.  This is useful because I can supply it to Hailang so that he can make the incrementation module be parameterized to be independent of the actual frequency that the system is running on.

Scheduling

According to the new schedule that was created as part of the interim midpoint demo I am still on track for the work that needed to be completed.  The only issue is that one of the weeks for doing work coming up is Carnival which hopefully will not conflict too heavily with progress on the project.

Team Report Mar. 30

Progress

This week as a team we worked on integrating all of our different pieces together to make a full pipeline from the keyboard being pressed until sound is produced. We managed to make two ends work, but as of today are still working on finalizing the last pieces of combining the DAC/Analog and the MIDI/keyboard. As we work for the next day-ish before our midterm demo, we intend to complete the pipeline so that we will at least hear some type of sound at the end of the day tomorrow.

One of the big issues that we are uncertain about is that we may need a digital low pass filter before we send our signal to the DAC to remove higher frequencies from our signal that we do not want to hear. This is currently the biggest risk that we foresee in our near future.

Scheduling

We are currently effectively on schedule, since we have managed to nearly finish integration for our project and once we have a single note that can be played through the pipeline, we should be able to play any given note that we want. This removes a couple weeks at the end of our schedule for integration and gives them to us now, which is why we are effectively on schedule at this point in the semester.

Jens’ Mar. 30th Status Report

Progress

This week I worked on integrating the modules that I had designed with the rest of the system and actually putting them onto the FPGA.  Currently as it stands the components through the wave tables have been connected to the system and have been tested to work with the MIDI messages that we can now read on the FPGA.  Additionally I helped Charles a little with the other end of the circuit getting the filters constructed and tested and getting a signal to pass through the DAC and be converted to analog.  Moving forward from here we hope to have a MIDI controlled sound driven through the system in time for the midterm demo.

Scheduling

According to the new version of the schedule we are now decently back on track with the coming weeks being fine tuning of the system and addition of the new components for the final iteration

 

Team Mar. 23 Status Report

Progress

This week we were all individually tasked with completing the first pass of all of the sections of the pipeline that we were responsible for in preparation for the midterm demo.  This meant that Charles worked on completing the FPGA interface with the DAC and the on board connection layout for this purpose. Hailang was tasked with making sure the UART decode and the MIDI message construction, and the support circuitry for the MIDI signal was ready for the midterm demo, while continuing work on the effects chain.  Jens worked on creating a simplified version of the digital synthesis pipeline. A few key features are being added latter for the purpose of having as functional a midterm demo as possible. The goal for the midterm demo is to have a single note be able to be played through the system from keyboard press to DAC output.  This coming up week is going to be spent finalizing all of the modules for this purpose and connecting them all together for the midterm demo version of the project.

Scheduling

This is slightly behind schedule from where we would have originally liked to have been because we overestimated how much time we would have before the midterm demo for the project.  The schedule has been slightly shifted around to move some portions of the project to after the midterm demo to make sure that the parts that we are aiming to include all work as intended. Many of the features that are to be added after this first iteration of the synthesizer, such as the polyphony, are scaled up versions of the modules that will be included in the midterm demo.  As a result the modules for this pass of the synthesizer will be designed for adaptation to the final version in mind.

Jens’ Mar. 23 Status Report

Progress

This week for the project I worked on getting a functioning version of the digital synthesis pipeline working.  This version of the pipeline involved a scaled back synthesis engine from the one that will be implemented for the final project.  Where the final version will support 4 note polyphony the goal for this first version is to have a single note be detected decided and the proper samples fetched and sent to the DAC.  For the most part this just simplifies the path to focus on one sample being fetched at a time instead of 4. This is then rather simple to scale back up to 4 notes once working. The one area where the scaling to multiple notes is less simple is in the logic that remembers which notes are being played at a given time and decides which note to throw away should an extra note be played.  This will be the focus of my work going forward, getting this module to function in the way that we want it to. In initial designs the difficulty was in keeping track of the priority of which note to be replaced, and specifically updating priority for the notes still being held once a note is released.

Scheduling

Moving forward with scheduling it is much more tight than I would have liked it to be.  There is still slack at the end of the semester to run into but at the moment I am behind schedule.  Once the midterm demo version of the project is complete I am going to ask the other group members if they are on track and if they can pick up some of the work on the mixer portion of the synthesis chain.  Hopefully this will help to get my allotted portion of the project back on task.

Jens’ Mar. 9 Status Report

Work Update

This week the entirity of my bandwidth for capstone for the front end of the week was consumed by writting my portion of the Design Document. This ended up taking considerably more time than was expected to complete as certain parts of the formatting did not want to play nice with inserting new figures and copying over text from Google Docs where we could colaborate as a team on the document. After the Design Document was due I had a lot of work in my other classes leading in to spring break and was completely swampped. As a result of this and the amount of time that the design document took, I was unable to complete most of the work that I had hoped to complete this week. This included writing the first pass of all of the verilog modules for the wavetable synthesis portion of the pipeline and creating the pakage file for sending translated MIDI control messages.

Scheduling

Now that I am behind schedule from the progress that I had hoped to make last week I have lost the bit of slack that I had gained from weeks prior. In addition despite the fact that this coming up week is Spring Break and I am going to be in London having fun for the duration of the week, I am going to have to try and take time out from siteseeing and watching soccer games to write the verilog files for this project. This means that for the coming up week I hope to have the first pass at the verilog files complete and have to complete the ethics case study for next weeks class as well.