Author: Charles Li

Progress

This week, I fixed an issue with ADSR that allowed the volume to go too low and caused some minor issues with our sound quality. I also worked with Hailang and we together found the issue that was causing our sound to be bad, as our DAC module wasn’t playing very well with the rest of our design because we added several pipeline stages to ensure that we met timing. This caused my DAC sender to then try to send two different samples in the same window sometimes, which meant that the DAC was getting a mixed sample. We also found an issue with our wavetable where one of the values was never specified (we had 1023 instead of 1024 values). I’ve spent much fo the week slowly soldering our filter bank to nicer protoboards that will improve our overall presentation.

Scheduling

In terms of scheduling, we’re a bit behind with polishing taking over a lot of the time that we had wanted to spend on the paper, but we will have a lot of dedicated time for the paper once we finish polishing our demo.

Progress

This week we added in the ADSR module, which worked exactly as intended, and attempted to add in all of the filtering circuitry to the rest of the analog components (MIDI reader and DAC sender). The filters all worked correctly, and were well within the 5% error margin that we had set for them. Unfortunately, for a reason that our team is still exploring, we cannot get a clean ground, which is causing problems in our output sounds. We have spent most of the week debugging this issue (among other smaller bugs) as a team.

Scheduling

In terms of scheduling, we just need to fix this bug, and since every individual part is tested, we simply need to run a couple of easy system tests once the bug is cleared. Additionally, we need to work on our poster and presentation tomorrow/Monday.

Progress

This week, I managed to finish wiring up and making look somewhat nice the filters and equalizer for our sound output. Only thing left to do are a couple of tests to check that they work as expected. I also managed to write up the rest of the ADSR module and wait for integration to determine how accurate it is.

Scheduling

In terms of scheduling, I just need to do some testing and I will be effectively on track for where I intended to be. This is likely to be done before demos start on Monday.

Progress

This week, I redesigned the filters and other circuitry with the lessons we had learned from our initial demo to work better (hopefully). These parts should be ordered by Tuesday, and then it’s a matter of checking that my calculations were correct and testing to ensure that we are within the metrics that we had set out for ourselves at the beginning of the project.

Scheduling

In terms of scheduling, I’m basically on schedule. I’ve done most of the heavy lifting for design (and re-design) and just need to implement now.

Progress

This week I finished building the DAC module that sends all of the clocking and data from the FPGA to the DAC and out to audio eventually. We ran into a bit of an issue since we had wanted to work with a 50MHz clock, but the FPGA GPIOs cannot handle that clock speed, we had to lower our clock speed slightly so that the DAC could read it. I also built and tested a few of the filters that I had designed and they work with a roughly 1% error in the 3dB point, as expected.

Scheduling

I’m roughly back on track, as I’ve caught up with where I should be on the schedule. We’ve already begun our testing and integration, so we’re a little bit ahead of schedule there.

Progress

This week I focused on the DAC Pre-Prep Module and fell sick for the second half of the week. I managed to write up a structure for the chipInterface on the FPGA and have it entirely functional for the ports that are needed for our design.

Scheduling

The sickness has set me a bit further behind, but as soon as I’m able to move around better without being sick.

Work Update

This week was spent for me mostly working on making sure that our design proposal was well laid out and making sure that the parts of it that were mine were presentable. This meant taking all of the design work I’ve done so far and combining it together into a readable format as well as continuing to explain and further flush out my ideas.

Scheduling

Due to the amount of work that I’ve had to put into overhead recently, I’ve fallen a little bit behind schedule, but expect to use Spring Break to catch back up to where I need to be.