Progress
This week I worked on several things, namely wavetable controllers and effects tuning.
We realized early this week that because the delay and reverb effects would use too much block RAM on the FPGA that it was no longer viable to make multiple copies of the same wavetable for multiple accesses. At each sample, we need to get a maximum of 8 sample values from the wavetable ROM but the block RAM is only two ported. Therefore, this week, I designed, implemented, and tested wrapper modules for the wavetable that would allow us to access an arbitrary number of wavetable entries at once and get all the data in a fixed delay some cycles later. For the wavetables, I also created modules that would generate simple wave shapes like sawtooth and triangle waves without needing the actual block RAMs.
On the effects end, I finished the design and implementation of the effects chain and have begun tuning. I wrote a Python script that would simulate the reverb module and allow me to quickly iterate through reverb parameter values in software to see what sounded good. I have found a set of parameters that sound good enough for now, although it’s not perfect and I may revisit reverb tuning later. I have also been running comparison tests in both Audacity and MATLAB to get a subjective comparison of what software reverb algorithms.
I have also worked on consolidating segments of the pipeline into a module hierarchy, because I want to try adding a simple recording+looping functionality that would be simple if the correct pieces of the synthesis pipeline are collected in a module that I can black-box and reuse. The main constraint of the recording and looping function is again the availability of block RAM on the device, although with the new wavetable wrappers and the revised reverb design, we should have enough block RAM to spare.
Scheduling
I am satisfied by the progress made this week and believe I am still on track overall for the endgame. My goal this week is to put the whole effects chain on the board and test on real hardware, although part of this is contingent on the analog parts arriving and the amplifier stage being finished.
