Progress
This week, I fixed an issue with ADSR that allowed the volume to go too low and caused some minor issues with our sound quality. I also worked with Hailang and we together found the issue that was causing our sound to be bad, as our DAC module wasn’t playing very well with the rest of our design because we added several pipeline stages to ensure that we met timing. This caused my DAC sender to then try to send two different samples in the same window sometimes, which meant that the DAC was getting a mixed sample. We also found an issue with our wavetable where one of the values was never specified (we had 1023 instead of 1024 values). I’ve spent much fo the week slowly soldering our filter bank to nicer protoboards that will improve our overall presentation.
Scheduling
In terms of scheduling, we’re a bit behind with polishing taking over a lot of the time that we had wanted to spend on the paper, but we will have a lot of dedicated time for the paper once we finish polishing our demo.
