Weekly Progress
This week I worked on the design presentation slides, preparing for the presentation, and creating block diagrams in digi-key’s design drawing tool. For the slides I work on all of the slides that covered aspects of my portion of the pipeline which is the digital synthesis section. The meat of this work was in creating the overall block diagram for this section. It was my first time using the digi-key diagram drawer and it took a little while to get used to. However now that I know how to use it, it is a very useful tool for creating standardized block diagrams. Additionally, I was the member of the group who gave the design presentation. Therefore, a good amount of my attention on capstone for the first half of the week was spent preparing for the presentation. This involved meeting with Zilei for a dry run of the presentation and running it myself multiple times. For the latter half of the week I spent time working on the digital synthesis sections of the design document as well as portions of the validation and verification sections.
Scheduling
I am currently on schedule for this week as our schedule added in a week of time budgeted to preparing the design presentation and the design document. My goals for next week are to tomorrow and Monday finish the design document. Additionally, I would like to get down a skeleton of all of the Verilog files I am going to be using for the digital synthesis portion of the pipeline. This includes a package and macros file where the types for the ports, such as note names and control knob names, will be defined for interfacing across the whole system. This may conflict with what is currently on the schedule for me to complete for next week however because it is work that goes towards all of the parts of the pipeline I want it to be completed first so at least all of my interfaces are well designed.
