Changes to the Design
Last week one of the large changes to the design that we were considering was the implementation of the wavetables in either the SDRAM on the FPGA or in the LUTs of the FPGA. After design work and deliberation this week we realized that we had neglected to consider a different option of using the block RAM on the FPGA. After running a series of tests to determine how much of this block RAM would be necessary to implement the features that we wish to use memory for we decided that for the board that we are planning to use placing the wavetables in block RAM is the best solution. See Hailang’s weekly report for more details regarding these changes.
Risks
Moving forward a big risk that is becoming apparent is in underestimating the difficulty of the tasks and interfacing between different elements of the project. For example during the more in depth design process it became clear to us that there would be an issue with interfacing the sample generation component with the effects and DAC because they operated at different clock frequencies. This was an issue that we had thought about but not on a deep enough level to understand some of the unforeseen issues involved. The two clocks that we had intended to use were a 50 mHz system clock and a 44.1kHz clock for the effects and DAC. However 50mHz is not evenly divisible by 44.1kHz so this would lead to issues. We believe that this can be dealt with by using the onboard PLLs to generate a system clock that is evenly divisible. However this is just an example of the integration and design consistency risk that we foresee going forward.
Schedule
Currently there have been no modifications to the schedule.
