Xiran’s Status Report for 9/25

I spent this week researching FPGA communication protocols. I was assigned USB, so I started with that. I found the following key pieces of information from the DE2-115 User Manual:

  • The board provides a USB device interface, supporting data transfer at 12 Mbit/s
  • There’s a demo with complete driver code that connects the board to a host PC and allows the PC to control some components on the board (such as LEDs)

I dug for user-side information on this topic too (e.g., customized driver code) but was not able to find much. This lack of information makes the usability of USB concerning to me, so I also looked into Ethernet. Surprisingly, I was able to find an open-source Cornell project that implemented Ethernet communication to the board. This may be something we can use off the shelf.

I am on schedule for my deliverables. Next week, I will transition to designing the ISA for our DUT. My thoughts so far are to limit the design to an ALU that supports common arithmetic and logical instructions, but details (instruction format, number of registers, etc.) need to be worked out. By the end of next week, I plan to have the complete ISA and to have begun working on the software golden model that implements this ISA.

Xiran’s Status Report for 9/18

I spent the majority of this week continuing to brainstorm project ideas. I looked into papers describing image processing and AI acceleration on FPGAs, before we settled on our idea on Wednesday. I then searched online and found many sources describing similar ideas (e.g., FPGA based accelerator for functional simulation, FPGA-accelerated evaluation and verification of RTL designs), which helped us confirm the validity of the use case and solution.

On Friday, I, along with my teammates, met with Prof. Bill Nace to discuss this idea further. I also set up the website. This weekend, I will help make the proposal slides. I am on schedule to meeting deliverables.

Next week, I will research communication protocols to send data to and obtain data from the FPGA. We should settle on one feasible protocol and begin implementing/benchmarking it.